Verilog中的TIming Loop

Question

我试图在Basys3板上用Verilog编写秒表。我写Verilog的经验很少。

`timescale 1ns / 1ps
    module seg7decimal(
        input [15:0] x,
        input clk,
        input clr,
        output reg [6:0] a_to_g,
        output reg [3:0] an,
        output wire dp 
         );


    wire [1:0] s;    
    reg [3:0] digit;
    wire [3:0] aen;
    reg [19:0] clkdiv;

    assign dp = 1;
    assign s = clkdiv[19:18];
    assign aen = 4'b1111; // all turned off initially

    // quad 4to1 MUX.

    reg [15:0] reg_d = 0;

    reg [3:0] temp_d0 = 4'b0000, temp_d1 = 4'b0000, temp_d2 = 4'b0000, temp_d3 = 4'b0000;
    reg [26:0] one_sec_cou

nter = 27'b000000000000000000000000000;

always @(posedge clk)
begin
    one_sec_counter = one_sec_counter + 1;
end

always @(one_sec_counter == 0)
begin
    if(temp_d0 == 9) // if count is xxx9 
    begin
        temp_d0 <= 0; //assign count0 to 0 
        if (temp_d1 == 9) //if count is xx99
        begin
            temp_d1 <= 0; //assign count1 to 0
            if (temp_d2 == 9) // if count is x999
            begin 
                temp_d2 <= 0; // assign count2 to 0  
                if(temp_d3 == 9) //if count is 9999
                    temp_d3 <= 0; //assign count3 to 0 
                else
                    temp_d3 <= temp_d3 + 1; //else case for count 9999 
            end 
            else //else case for count x999
                temp_d2 <= temp_d2 + 1;
         end 
         else //else case for count xx99
            temp_d1 <= temp_d1 + 1; 
    end
    else
        temp_d0 = temp_d0 + 1;
//      reg_d = reg_d + 1;
end

always @(posedge clk)
begin
    reg_d[3:0] = temp_d0;
    reg_d[7:4] = temp_d1;
    reg_d[11:8] = temp_d2;
    reg_d[15:12] = temp_d3;
end


always @(posedge clk)// or posedge clr)

    case(s)
    0:digit = reg_d[3:0]; // s is 00 -->0 ;  digit gets assigned 4 bit value assigned to x[3:0]
    1:digit = reg_d[7:4]; // s is 01 -->1 ;  digit gets assigned 4 bit value assigned to x[7:4]
    2:digit = reg_d[11:8]; // s is 10 -->2 ;  digit gets assigned 4 bit value assigned to x[11:8
    3:digit = reg_d[15:12]; // s is 11 -->3 ;  digit gets assigned 4 bit value assigned to x[15:12]

    default:digit = reg_d[3:0];

    endcase

    //decoder or truth-table for 7a_to_g display values


always @(*)

case(digit)


//////////<---MSB-LSB<---
//////////////gfedcba////////////////////////////////////////////              a
0:a_to_g = 7'b1000000;////0000                                                 __                   
1:a_to_g = 7'b1111001;////0001                                              f/    /b
2:a_to_g = 7'b0100100;////0010                                                g
//                                                                           __ 
3:a_to_g = 7'b0110000;////0011                                           e /   /c
4:a_to_g = 7'b0011001;////0100                                               __
5:a_to_g = 7'b0010010;////0101                                               d  
6:a_to_g = 7'b0000010;////0110
7:a_to_g = 7'b1111000;////0111
8:a_to_g = 7'b0000000;////1000
9:a_to_g = 7'b0010000;////1001
'hA:a_to_g = 7'b0111111; // dash-(g)
'hB:a_to_g = 7'b1111111; // all turned off
'hC:a_to_g = 7'b1110111;

default: a_to_g = 7'b0000000; // U

endcase


always @(*)begin
an=4'b1111;
if(aen[s] == 1)
an[s] = 0;
end


//clkdiv

always @(posedge clk or posedge clr) begin
if ( clr == 1)
clkdiv <= 0;
else
clkdiv <= clkdiv+1;
end


endmodule

由于某种原因，它在第2行“发现时序循环”和比特流生成中始终显示严重警告

[Synth 8-295]找到了定时循环。 [“ /home/2017csb1113/Desktop/proj/7segdisplay/7segdisplay.srcs/sources_1/new/7seg.v":2]