16位数乘法

时间:2012-05-17 09:30:39

标签: binary logic vhdl

在这段代码中,我试图将16位数字相乘并获得32位输出。代码有错误。在行

    c<=c+a;

编译器发出错误:“无法读取模式输出端口'c'。我的错误是什么?谢谢。

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity circ is
    port (  a    :in std_logic_vector (15 downto 0);
    b    :in std_logic_vector (15 downto 0);
    c    :out  std_logic_vector (31 downto 0)
        );

    end entity;

    architecture data of circ is
    begin
process(a,b)
begin
c<= '0';   
for i in 15 to 0 loop
if (b(i) = '1') then
c<=c+a;
end if;
END LOOP;

end process;
    end data;

1 个答案:

答案 0 :(得分:1)

错误正是编译器告诉你的错误

  

无法读取模式输出端口'c'

您无法读取输出。当您撰写c时,您正在阅读c <= c + a,因为c出现在作业的右侧。你必须重写这样的代码:

signal s : std_logic_vector(31 downto 0);

process(a,b)
begin
  s <= (others => '0');   
  for i in 15 to 0 loop
    if (b(i) = '1') then
      s <= s + a; -- Use a local signal that we can read and write
    end if;
  end loop;
  c <= s; -- Assign the output to the local signal.
end process;