Question

我需要一个触发器，它对两个不同信号的边缘作出反应。像这样：

if(rising_edge(sig1)) then
    bit <= '0';
elsif(rising_edge(sig2)) then
    bit <= '1';
end if;

这样的触发器是否存在或者是否有其他可以使用的技术？我需要在Xilinx Virtex-5 FPGA上进行综合。感谢

Answer 1

在这种情况下，我通常做的是保持两个控制信号的延迟版本，并在每个信号的上升沿产生一个时钟宽的脉冲。然后，我将使用这些脉冲驱动一个微小的FSM来产生“比特”信号。这是下面的一些VHDL。

--                                         -*-vhdl-*-
--  Finding edges of control signals and using the
-- edges to control the state of an output variable
--

library ieee;
use ieee.std_logic_1164.all;

entity stackoverflow_edges is
  port ( clk  : in std_ulogic;
     rst  : in std_ulogic;
     sig1 : in std_ulogic;
     sig2 : in std_ulogic;
     bito : out std_ulogic );

end entity stackoverflow_edges;

architecture rtl of stackoverflow_edges is

  signal sig1_d1  , sig2_d1   : std_ulogic;
  signal sig1_rise, sig2_rise : std_ulogic;

begin 

  -- Flops to store a delayed version of the control signals
  -- If the contorl signals are not synchronous with clk,
  -- consider using a bank of 2 delays and using those outputs
  -- to generate the edge flags
  delay_regs: process ( clk ) is 
  begin 
    if rising_edge(clk) then
      if rst = '1' then 
        sig1_d1 <= '0';
        sig2_d1 <= '0';
      else
        sig1_d1 <= sig1;
        sig2_d1 <= sig2;
      end if;
    end if;
  end process delay_regs;


  -- Edge flags
  edge_flags: process (sig1, sig1_d1, sig2, sig2_d1) is
  begin
    sig1_rise <= sig1 and not sig1_d1;
    sig2_rise <= sig2 and not sig2_d1;
  end process edge_flags;

  -- Output control bit
  output_ctrl: process (clk) is
  begin 
    if rst = '1' then
      bito <= '0';
    elsif sig1_rise = '1' then
      bito <= '1';
    elsif sig2_rise = '1' then
      bito <= '0';
    end if;
  end process output_ctrl;

end rtl;

我在verilog中更舒服，所以仔细检查这个VHDL（任何评论赞赏）。

waveforms http://img33.imageshack.us/img33/893/stackoverflowvhdlq.png

此代码假定时钟足够快以捕获所有控制信号脉冲。如果控制信号与时钟不同步，我将保留延迟控制信号的进一步延迟版本（例如sig_d2），然后从sig_d1和sig_d2。

触发器在两个信号的边缘触发

1 个答案: