Question

多年后我正在重新审视VHDL。我试图在某个溢出周期设置一个带有计数器触发器的基本状态机。

出于某种原因，我在m_tick时钟的下降沿获得状态转换。基于状态过程中的m_tick＆lt; ='1'，只应在上升沿进行转换？我必须忽视一些事情。

我在isim测试。我相信我可能做的不是很聪明。

感谢。

entity nes_ctl is
generic(
        N: integer :=  3;       --17 bit overflow 131k
 );
port(
        clk : in std_logic;
        n_reset : in std_logic
);
end nes_ctl;

architecture Behavioral of nes_ctl is

signal count_reg, count_next: unsigned(N-1 downto 0);   --counter to produce tick
signal m_tick: std_logic;
--state variable
type state_type is (s0,s1,s2,s3,s4,s5);
signal state_reg, state_next: state_type;
signal reset: std_logic;    --inverted reset signal

begin

reset <= not(n_reset);  --invert the reset signal

--syncronos logic
process(clk)
begin
    if(reset= '1') then
        count_reg <= (others=>'0');
        state_reg <= s0;
    elsif (clk'event and clk = '1') then
        count_reg <= count_next;
        state_reg <= state_next;
    end if;
end process;

count_next <= count_reg +1;     --increment counter, will overflow
m_tick <= '1' when count_reg = 0 else '0';      -- tick on every overflow

--STATE MACHINE
process(m_tick)
begin
    if(m_tick <= '1') then  --only when m_tick goes high
        case state_reg is
            when s0 =>
                state_next <= s1;
            when s1 =>
                state_next <= s2;
            when s2 =>
                state_next <= s3;
            when s3 =>
                state_next<= s4;
            when s4 =>
                state_next<= s5;
            when s5 =>
                state_next <= s0;
        end case;   
    else 
        state_next <= state_reg; --keep same state.  no       latches.
    end if;
end process;


end Behavioral;

Answer 1

只要m_tick为低，

m_tick＆lt; ='1'就为真，而不仅仅是上升沿。如果您打算使用m_tick作为时钟，则需要使用m_tick'event和m_tick ='1'，就像使用clk一样。如果您打算将m_tick的上升沿作为时钟使能信号，则需要使用clk信号为进程计时，并通过将其与延迟版本进行比较来检测m_tick的上升沿：

process(clk)
begin
    if (clk'event and clk = '1') then
        m_tick_q <= m_tick;

        -- only when m_tick goes high
        if m_tick='1' and m_tick_q='0' then
            case state_reg is
            ...

状态转变下降边缘

1 个答案: