Question

我可以在VHDL中使用类似于C-Sourcecode-Macros __DATE__和__TIME__的内容在FPGA中将编译时间作为一种版本时间戳？

作为＆gt;＆gt;＆gt; new-comer＆lt;＆lt;＆lt;＆lt;到VHDL我想修改以下现有代码，它将硬编码日期放入FPGA寄存器。我总是要记住在编译之前调整值。如果这是自动完成的话会更容易。我还可以包括小时/分钟/秒吗？

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Datum2 IS
   PORT
   (
        Day         :OUT std_logic_vector(4 downto 0);
        Month       :OUT std_logic_vector(3 downto 0);
        Year        :OUT std_logic_vector(4 downto 0)
   );
END Datum2 ;

ARCHITECTURE rtl OF Datum2 IS

BEGIN
--  "08.08.0013"
    Day   <= conv_std_logic_vector(8, 5);
    Month <= conv_std_logic_vector(8, 4);
    Year  <= conv_std_logic_vector(13, 5);
END ARCHITECTURE rtl;

Answer 1

当前日期和时间不能直接在VHDL中使用，但建议在下面提供解决方案。

EDITED 2013-08-10 ：添加了Altera Quartus II Tcl自动生成的说明。

提供日期和时间的一种方法是通过自动生成的VHDL包，如下所示：

library ieee;
use ieee.std_logic_1164.all;

package datetime is
  -- Date information
  constant YEAR_INT  : integer                       := 2013;
  constant YEAR_HEX  : std_logic_vector(15 downto 0) := X"2013";
  constant MONTH_INT : integer                       := 08;
  constant MONTH_HEX : std_logic_vector(7 downto 0)  := X"08";
  constant DAY_INT   : integer                       := 09;
  constant DAY_HEX   : std_logic_vector(7 downto 0)  := X"09";
  constant DATE_HEX  : std_logic_vector(31 downto 0) := YEAR_HEX & MONTH_HEX & DAY_HEX;
  -- Time information
  constant HOUR_INT   : integer                       := 13;
  constant HOUR_HEX   : std_logic_vector(7 downto 0)  := X"13";
  constant MINUTE_INT : integer                       := 06;
  constant MINUTE_HEX : std_logic_vector(7 downto 0)  := X"06";
  constant SECOND_INT : integer                       := 29;
  constant SECOND_HEX : std_logic_vector(7 downto 0)  := X"29";
  constant TIME_HEX   : std_logic_vector(31 downto 0) := X"00" & HOUR_HEX & MINUTE_HEX & SECOND_HEX;
  -- Miscellaneous information
  constant EPOCH_INT  : integer := 1376046389;  -- Seconds since 1970-01-01_00:00:00
end package;

可以使用如下的Tcl脚本创建此VHDL包：

# Make datetime.vhd package from Tcl script

# Current date, time, and seconds since epoch
# Array index                                            0  1  2  3  4  5  6
set datetime_arr [clock format [clock seconds] -format {%Y %m %d %H %M %S %s}]

# Write VHDL package
set filename datetime.vhd
set file [open $filename w]
puts $file "library ieee;"
puts $file "use ieee.std_logic_1164.all;"
puts $file ""
puts $file "package datetime is"
puts $file "  -- Date information"
puts $file "  constant YEAR_INT  : integer                       := [lindex $datetime_arr 0];"
puts $file "  constant YEAR_HEX  : std_logic_vector(15 downto 0) := X\"[lindex $datetime_arr 0]\";"
puts $file "  constant MONTH_INT : integer                       := [lindex $datetime_arr 1];"
puts $file "  constant MONTH_HEX : std_logic_vector(7 downto 0)  := X\"[lindex $datetime_arr 1]\";"
puts $file "  constant DAY_INT   : integer                       := [lindex $datetime_arr 2];"
puts $file "  constant DAY_HEX   : std_logic_vector(7 downto 0)  := X\"[lindex $datetime_arr 2]\";"
puts $file "  constant DATE_HEX  : std_logic_vector(31 downto 0) := YEAR_HEX & MONTH_HEX & DAY_HEX;"
puts $file "  -- Time information"
puts $file "  constant HOUR_INT   : integer                       := [lindex $datetime_arr 3];"
puts $file "  constant HOUR_HEX   : std_logic_vector(7 downto 0)  := X\"[lindex $datetime_arr 3]\";"
puts $file "  constant MINUTE_INT : integer                       := [lindex $datetime_arr 4];"
puts $file "  constant MINUTE_HEX : std_logic_vector(7 downto 0)  := X\"[lindex $datetime_arr 4]\";"
puts $file "  constant SECOND_INT : integer                       := [lindex $datetime_arr 5];"
puts $file "  constant SECOND_HEX : std_logic_vector(7 downto 0)  := X\"[lindex $datetime_arr 5]\";"
puts $file "  constant TIME_HEX   : std_logic_vector(31 downto 0) := X\"00\" & HOUR_HEX & MINUTE_HEX & SECOND_HEX;"
puts $file "  -- Miscellaneous information"
puts $file "  constant EPOCH_INT  : integer := [lindex $datetime_arr 6];  -- Seconds since 1970-01-01_00:00:00"
puts $file "end package;"
close $file

在Altera Quartus II中，可以在合成之前使流程运行此脚本，从而可以创建datetime包。这是在.qsf文件中使用下面的行完成的，其中脚本名为“make_datetime.tcl”：

set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:make_datetime.tcl"

可以在Quartus II Tcl Example: Automatic Script Execution中找到对Quartus II功能的进一步描述。

然后，Datum2模块可以使用这样的包：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity Datum2 is
  port(
    Day   : out std_logic_vector(4 downto 0);
    Month : out std_logic_vector(3 downto 0);
    Year  : out std_logic_vector(4 downto 0));
end Datum2;


library work;
use work.datetime;

architecture rtl of Datum2 is
begin
  Day   <= conv_std_logic_vector(datetime.day_int, 5);
  Month <= conv_std_logic_vector(datetime.month_int, 4);
  Year  <= conv_std_logic_vector(datetime.year_int mod 100, 5);
end architecture rtl;

在Quartus II中合成后，RTL查看器显示模块输出如下：

enter image description here

之前描述的替代解决方案是使用像这样的Bash脚本创建VHDL包：

# Make datetime.vhd package from shell script

# Current date, time, and seconds since epoch
# Array index           0  1  2  3  4  5  6
datetime_arr=($(date +"%Y %m %d %H %M %S %s"))

# Write VHDL package
filename="datetime.vhd"
echo "library ieee;" > $filename
echo "use ieee.std_logic_1164.all;" >> $filename
echo "" >> $filename
echo "package datetime is" >> $filename
echo "  -- Date information" >> $filename
echo "  constant YEAR_INT  : integer                       := ${datetime_arr[0]};" >> $filename
echo "  constant YEAR_HEX  : std_logic_vector(15 downto 0) := X\"${datetime_arr[0]}\";" >> $filename
echo "  constant MONTH_INT : integer                       := ${datetime_arr[1]};" >> $filename
echo "  constant MONTH_HEX : std_logic_vector(7 downto 0)  := X\"${datetime_arr[1]}\";" >> $filename
echo "  constant DAY_INT   : integer                       := ${datetime_arr[2]};" >> $filename
echo "  constant DAY_HEX   : std_logic_vector(7 downto 0)  := X\"${datetime_arr[2]}\";" >> $filename
echo "  constant DATE_HEX  : std_logic_vector(31 downto 0) := YEAR_HEX & MONTH_HEX & DAY_HEX;" >> $filename
echo "  -- Time information" >> $filename
echo "  constant HOUR_INT   : integer                       := ${datetime_arr[3]};" >> $filename
echo "  constant HOUR_HEX   : std_logic_vector(7 downto 0)  := X\"${datetime_arr[3]}\";" >> $filename
echo "  constant MINUTE_INT : integer                       := ${datetime_arr[4]};" >> $filename
echo "  constant MINUTE_HEX : std_logic_vector(7 downto 0)  := X\"${datetime_arr[4]}\";" >> $filename
echo "  constant SECOND_INT : integer                       := ${datetime_arr[5]};" >> $filename
echo "  constant SECOND_HEX : std_logic_vector(7 downto 0)  := X\"${datetime_arr[5]}\";" >> $filename
echo "  constant TIME_HEX   : std_logic_vector(31 downto 0) := X\"00\" & HOUR_HEX & MINUTE_HEX & SECOND_HEX;" >> $filename
echo "  -- Miscellaneous information" >> $filename
echo "  constant EPOCH_INT  : integer := ${datetime_arr[6]};  -- Seconds since 1970-01-01_00:00:00" >> $filename
echo "end package;" >> $filename

对于平台独立性，可以使用这样的Python 3.x脚本：

# Make datetime.vhd package from Python 3.x script

# Get date and time
import datetime
import time
now = datetime.datetime.now()
now_epoch_sec = int(time.time())

# Write VHDL package
file = open('datetime.vhd', 'wt')
file.write('library ieee;\n')
file.write('use ieee.std_logic_1164.all;\n')
file.write('\n')
file.write('package datetime is\n')
file.write('  -- Date information\n')
file.write('  constant YEAR_INT  : integer                       := {};\n'.format(now.strftime('%Y')))
file.write('  constant YEAR_HEX  : std_logic_vector(15 downto 0) := X\"{}\";\n'.format(now.strftime('%Y')))
file.write('  constant MONTH_INT : integer                       := {};\n'.format(now.strftime('%m')))
file.write('  constant MONTH_HEX : std_logic_vector(7 downto 0)  := X\"{}\";\n'.format(now.strftime('%m')))
file.write('  constant DAY_INT   : integer                       := {};\n'.format(now.strftime('%d')))
file.write('  constant DAY_HEX   : std_logic_vector(7 downto 0)  := X\"{}\";\n'.format(now.strftime('%d')))
file.write('  constant DATE_HEX  : std_logic_vector(31 downto 0) := YEAR_HEX & MONTH_HEX & DAY_HEX;\n')
file.write('  -- Time information\n')
file.write('  constant HOUR_INT   : integer                       := {};\n'.format(now.strftime('%H')))
file.write('  constant HOUR_HEX   : std_logic_vector(7 downto 0)  := X\"{}\";\n'.format(now.strftime('%H')))
file.write('  constant MINUTE_INT : integer                       := {};\n'.format(now.strftime('%M')))
file.write('  constant MINUTE_HEX : std_logic_vector(7 downto 0)  := X\"{}\";\n'.format(now.strftime('%M')))
file.write('  constant SECOND_INT : integer                       := {};\n'.format(now.strftime('%S')))
file.write('  constant SECOND_HEX : std_logic_vector(7 downto 0)  := X\"{}\";\n'.format(now.strftime('%S')))
file.write('  constant TIME_HEX   : std_logic_vector(31 downto 0) := X\"00\" & HOUR_HEX & MINUTE_HEX & SECOND_HEX;\n')
file.write('  -- Miscellaneous information\n')
file.write('  constant EPOCH_INT  : integer := {};  -- Seconds since 1970-01-01_00:00:00\n'.format(now_epoch_sec))
file.write('end package;\n')
file.close()

为了在32位寄存器值中显示日期和时间，模块可以是这样的：

library ieee;
use ieee.std_logic_1164.all;
entity tb is
end entity;

library work;
use work.datetime;
architecture sim of tb is
  signal date_hex : std_logic_vector(31 downto 0);
  signal time_hex : std_logic_vector(31 downto 0);
begin
  date_hex <= datetime.DATE_HEX;
  time_hex <= datetime.TIME_HEX;
  process is begin wait; end process;
end architecture;

波形如下所示。

enter image description here

Bash或Python脚本方法需要在构建流程中集成以自动生成包。

2016-08-08已更新，Damien更新：Altera Quartus的非Tcl脚本调用说明。

要集成bash脚本（在Linux下），请创建一个Tcl包装器脚本，该脚本在进程中调用bash脚本。在这个例子中，有一个“scripts”目录，它有一个“call_bash.tcl”脚本和一个“make_datetime.sh”来完成实际工作：

# Useful if the script is in a subdirectory
proc getScriptDirectory {} {
    set dispScriptFile [file normalize [info script]]
    set scriptFolder [file dirname $dispScriptFile]
    return $scriptFolder
}

set scriptDir [getScriptDirectory]

# Call the bash script which does the real work
exec $scriptDir/make_datetime_vhdl.sh

# Add a message the Altera workflow
post_message -type info "Created datetime.vhd"

然后可以通过在qsf文件中添加以下内容来实现与Altera的构建流程的集成：

set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:scripts/call_bash.tcl"

Answer 2

我使用64位std_logic_vector常量。

我有一个TCL脚本，它在合成之前运行，将当前时间编码为一个包中的常量，然后包含在FPGA中，以便以某种方式读出它。

我在模拟中使用了同一个软件包的非自动生成版本 - 这个没有更改，因此我不必继续更新测试。

Answer 3

每次更新时间戳时，您都不需要写出完整的代码。在Quartus中，您可以在编译之前使用TCL设置顶级泛型：

将泛型传递给时间戳实体：

entity top is
generic (day, month, year : integer);
end entity top;

architecture struct of top is
begin
timestamp_inst : entity work.timestamp generic map(day, month, year);
end architecture struct;

然后使用preflow脚本设置泛型：

set_parameter -name day $someday
set_parameter -name year $someyear
# etc

我已经成功地使用了这种方法，包括时间戳，git修订版，构建ID。我发现将它转换为字阵列然后作为ROM访问很方便。只要运用你的想象力。

在FPGA中结合日期和时间

3 个答案: