我正在测试用于读取文本文件的示例源代码:此文件的每一行包含两个整数(由空格分隔),必须一起读取和求和。在下面的代码中,我只报告架构。
architecture behav of tb is
signal xb, yb, zb: std_logic_vector(7 downto 0);
begin
process
file fp: text is in "in.txt";
variable ln: line;
variable x, y, z: integer;
begin
readline( fp, ln ); read( ln, x ); read( ln, y );
xb <= conv_std_logic_vector( x, 8 );
yb <= conv_std_logic_vector( y, 8 );
if endfile( fp ) = true then
wait;
else
wait for 10 ns;
end if;
end process;
DUT: zb <= xb + yb;
end behav;
编译源代码后,我运行模拟并继续正确到文本文件的末尾。但是,如果我更改源代码,如下所示,模拟不会在文本文件的末尾结束。为什么呢?
architecture behav of tb is
signal xb, yb, zb: std_logic_vector(7 downto 0);
begin
process
file fp: text is in "in.txt";
variable ln: line;
variable x, y, z: integer;
begin
while not endfile(fp) loop
readline( fp, ln ); read( ln, x ); read( ln, y );
xb <= conv_std_logic_vector( x, 8 );
yb <= conv_std_logic_vector( y, 8 );
wait for 10 ns;
end loop;
end process;
DUT: zb <= xb + yb;
end behav;