Question

我无法弄清楚如何取两个std_logic_vector的绝对值（31 downto 0）;

这是一个代码示例：

library ieee;
use ieee.std_logic_1164.all;        
use ieee.numeric_std.all;       -- for the signed, unsigned types and arithmetic ops
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
...
...
port (  
    X: in std_logic_vector(31 downto 0); 
    Y: in std_logic_vector(31 downto 0); 
    F: out std_logic_vector(31 downto 0) 
  );

..
..
..
process(X,Y)
 begin
 F <= abs(X-Y)     --this doesnt work

Answer 1

抛弃非标准库包含并使用具有内置signed函数的标准abs类型：

library ieee;
use ieee.std_logic_1164.all;        
use ieee.numeric_std.all; -- this is the standard package where signed is defined
-- never use non-standard ieee.std_logic_arith and ieee.std_logic_unsigned

...

port (  
  X: in  std_logic_vector(31 downto 0); 
  Y: in  std_logic_vector(31 downto 0); 
  F: out std_logic_vector(31 downto 0) 
);

...

process(X,Y) is
begin
  F <= std_logic_vector(abs(signed(X)-signed(Y)));
end process;

最后一行在std_logic_vector和signed之间进行了很多[可能不必要的]转换，所以如果对你的设计的其余部分有意义的话，你可能更喜欢这个界面：

port (  
  X: in  signed(31 downto 0); 
  Y: in  signed(31 downto 0); 
  F: out signed(31 downto 0) 
);

然后最后一行只是：

 F <= abs(X-Y);

如何获取std_logic_vector的绝对值？在VHDL中

1 个答案: