Case语句返回不正确的值

时间:2014-02-28 01:47:00

标签: verilog seven-segment-display

我正在尝试这样做7段显示功能。 输入“rn”是我想要显示的数字,但是当我在ISE套件上进行模拟时,它只能在等于0或1时识别“rn”。任何大于此值的值都将失败,所以输出seg [7:0]只是8位的0。

module LED_7seg(clk, btn, rn, segA, segB, segC, segD, segE, segF, segG, segDP, anodes);

input clk, btn;       
input [4:0] rn;
output [3:0] anodes;     

output segA, segB, segC, segD, segE, segF, segG, segDP;

wire [4:0] rn_in;
reg [7:0] seg;


assign {rn_in[4], rn_in[3], rn_in[2], rn_in[1], rn_in[0]} = rn;


always @ (*)
case (rn_in)
    (5'b00001 || 5'b10001) : seg = 8'b11111100;    //0
    (5'b00001 || 5'b10001) : seg = 8'b01100000;     //1
    (5'b00010 || 5'b10010) : seg = 8'b11011010;     //2
    (5'b00011 || 5'b10011) : seg = 8'b11110010;     //3
    (5'b00100 || 5'b10100) : seg = 8'b01100110;     //4
    (5'b00101 || 5'b10101) : seg = 8'b10110110;     //5
    (5'b00110 || 5'b10110) : seg = 8'b10111110;     //6
    (5'b00111 || 5'b10111) : seg = 8'b11100000;     //7
    (5'b01000 || 5'b11000) : seg = 8'b11111110;     //8
    (5'b01001 || 5'b11001) : seg = 8'b11110110;     //9
    (5'b01010 || 5'b11010) : seg = 8'b11101110;     //10
    (5'b01011 || 5'b11011) : seg = 8'b00111110;      //11
    (5'b01100 || 5'b11100) : seg = 8'b10011100;     //12
    (5'b01101 || 5'b11101) : seg = 8'b01111010;     //13
    (5'b01110 || 5'b11110) : seg = 8'b10011110;     //14
    (5'b01111 || 5'b11111) : seg = 8'b10001110;     //15
    default : seg = 8'b00000000; 
endcase

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = seg;

endmodule

任何帮助都会有所帮助。

1 个答案:

答案 0 :(得分:2)

您正在使用||运算符,这是逻辑或。在您的代码中,您正在计算两个非零值的逻辑OR,它总是计算为1.例如:(5'b00001 || 5'b10001)= 1.

我认为您想要的是以下内容:

更改(针对每个案例项目)

(5'b00001 || 5'b10001) : seg = 8'b11111100;    //0

成:

5'b00001, 5'b10001 : seg = 8'b11111100;    //0

前者表示rn_in等于(5'b00001 || 5'b10001)= 1。后者意味着如果rn_in等于5'b00001或者rn_in等于5'b10001。