Question

我想模拟寄存器逻辑，但测试台不工作，当影响输入信号＆＃34; Si，ECi，Ri，Ci＆＃34;时，所有信号输入固定为＆＃34 ; 0000000001＆＃34;当我在Xlinix中运行模拟时，输出固定为＆＃34; ZZZZZZZZ0＆＃34;我不知道为什么？

这里是注册

的代码vhdl

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity Registre is
    Generic ( N: positive :=10);
    Port ( R : in  STD_LOGIC_VECTOR (N downto 1);
           EC : in  STD_LOGIC_VECTOR (N downto 1); 
           C : in  STD_LOGIC_VECTOR (N downto 1);
           S : in  STD_LOGIC_VECTOR (N downto 1);
           Vss : in  STD_LOGIC_VECTOR (N downto 1);
           Vdd : in STD_LOGIC_VECTOR (N downto 1);
           DA : out  STD_LOGIC_VECTOR (N downto 1));
end Registre;

architecture Behavioral of Registre is

    component SA_REG 
        Port ( EC : in  STD_LOGIC;
               C : in  STD_LOGIC;
               R : in  STD_LOGIC;
               S : in  STD_LOGIC;
               Q : out  STD_LOGIC;
               Vss : in  STD_LOGIC;
               Vdd : in  STD_LOGIC);
    end component;

    Component SA_REGDR
        Port ( R : in  STD_LOGIC;
               C : in  STD_LOGIC;
               EC : in  STD_LOGIC;
               Q : out  STD_LOGIC;
               Vss: in STD_LOGIC;
               Vdd: in STD_LOGIC
           );
    end component;

begin

    DR : SA_REGDR port map ( R=> R(10) ,EC=> EC(10), C=> C(10), Vss=> Vss(10), Vdd=> Vdd(10), Q=> DA(10) );

    Mgen : for i in 1 to N-1 generate
        M : SA_REG port map (R=>R(i), EC=> EC(i), C=> C(i),S=> S(i), Vss=> Vss(i), Vdd=> Vdd(i), Q=> DA(i) ); 
    end generate;

end Behavioral;

试验台：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity Registre_tb is
end Registre_tb;

architecture Behavioral of Registre_tb is
    component Registre
        generic( N : integer :=10);
        Port ( R : in  STD_LOGIC_VECTOR (10 downto 1);
               EC : in  STD_LOGIC_VECTOR (10 downto 1);
               C : in  STD_LOGIC_VECTOR (10 downto 1);
               S : in  STD_LOGIC_VECTOR (10 downto 1);
               Vss : in  STD_LOGIC_VECTOR (10 downto 1);
               Vdd : in STD_LOGIC_VECTOR (10 downto 1);
               DA : out  STD_LOGIC_VECTOR (10 downto 1));
    end component;

    signal  Ri  : STD_LOGIC_VECTOR (10 downto 1):= (others => '0');
    signal  Ci  : STD_LOGIC_VECTOR (10 downto 1):= (others => '0');
    signal  ECi : STD_LOGIC_VECTOR (10 downto 1):= (others => '0');
    signal  Si  : STD_LOGIC_VECTOR (10 downto 1):= (others => '0');
    signal  Vssi: STD_LOGIC_VECTOR (10 downto 1):= (others => '0');
    signal  Vddi: STD_LOGIC_VECTOR (10 downto 1):= (others => '1');
    signal  DAi : STD_LOGIC_VECTOR (10 downto 1);

    signal clk : std_logic := '0';
begin
    -- instanciate 
    component_in_test : Registre port map( --instantiation of the Registre component
        R => Ri,
        C => Ci,
        EC => ECi,
        S => Si,
        Vss => Vssi,
        Vdd => Vddi,
        DA => DAi
    );

    -- stimulis 
    clk <= not clk after 1ns; --creates 100MHz clock inside testbench

    Ri_gen : process(clk) is   --process which will check Ri with every possible value
    begin
        if clk'Event and clk = '1' then
            Ri <= Ri + 1;
        end if;
    end process;

    Ci_gen : process(clk) is   --process which will check Ci with every possible value
    begin
        if clk'Event and clk = '1' then
            Ci <= Ci + 1;
        end if;
    end process;

    ECi_gen : process(clk) is   --process which will check ECi with every possible value
    begin
        if clk'Event and clk = '1' then
            ECi <= ECi + 1;
        end if;
    end process;

    Si_gen : process(clk) is   --process which will check Si with every possible value
    begin
        if clk'Event and clk = '1' then
            Si <= Si + 1;
        end if;
    end process;

end Behavioral;

模拟 enter image description here

Answer 1

请参阅VHDL常见问题解答中关于最长静态前缀的讨论：http://www.eda.org/comp.lang.vhdl/FAQ1.html#drivers

因此，您需要将实例重写为：

Mgen  : for i in 1 to N generate  
  If_N : if i = N generate
    DR : SA_REGDR port map ( R=> R(10) ,EC=> EC(10), C=> C(10), Vss=> Vss(10), Vdd=> Vdd(10), Q=> DA(10) ); 
  end generate ; 

  if_OTHERS : if i /= N generate
    M : SA_REG port map (R=>R(i), EC=> EC(i), C=> C(i),S=> S(i), Vss=> Vss(i), Vdd=> Vdd(i), Q=> DA(i) ); 
  end generate ; 
end generate;

Answer 2

调试=将问题减少到最小。关于VHDL，您可以将所有内容实例化为实体，例如

U1: entity MY_IMPLEMENTATION port map ()

为了消除在任何地方声明组件的需要。您可以公开其实现，而不是声明SA_REG和SA_REGDR组件。

您的SA_REGDR卡在第10位，而N用于SA_REG实例化是可变的。你正在为不一致做准备。

输出DA（i）由SA_REG和SA_REGDR确定，其实现保密。因此，我们无法回答这个问题。然而，＆＃39; z＆＃39;值意味着其中一个输入是driver enable。当您递增输入时，输入的较低有效位开关0 - > 1和它的驱动器被启用，以便最低有效输出位切换高阻抗=＆gt;具体价值。没有足够的信息来解释为什么你在LSB而不是1或其他任何东西中得到0。

Actually, other signals can stay unresolved。只有DA（i）必须是std_logic。

VHDL Testbench代码不适用于注册

2 个答案: