交通VHDL模拟问题

时间:2014-10-19 16:33:43

标签: vhdl

我已更新程序,它确实完成但现在我正在尝试模拟项目。我能够清除时钟并点亮引脚,但是我无法让灯工作并计数和状态甚至不显示。我相信我已经正确设置了这一切,但我可​​能错了。再次感谢Morten Zilmer对错误代码的帮助。

http://tinypic.com/r/24yog0z/8

这是文件的模拟, simulation image

entity traffic is
port    (clk: in std_logic;
         clr: in std_logic;
         lights: out std_logic_vector (5 downto 0));
 end traffic;

 architecture traffic of traffic is
 type state_type is (s0, s1, s2, s3, s4, s5);
 signal state: state_type;
 signal count : std_logic_vector (3 downto 0);
 constant sec5: std_logic_vector (3 downto 0) := "1111";
 constant sec1: std_logic_vector (3 downto 0) := "0011";

 begin
 process(clk, clr)
 begin
if clr = '1' then
        state<= s0;
        count <= x"0";
elsif (clk'event and clk = '1') then
    case state is
    when s0 =>
        if count <= sec5 then
            state <= s0;
            count <= count +1;
        else
            state <= s1;
            count <= x"0";
            end if;
    when s1 =>
        if count <= sec1 then
            state <= s1;
            count <= count +1;
        else
            state <= s2;
            count <= x"0";
            end if;
    when s2 =>
        if count <= sec1 then
            state <= s2;
            count <= count +1;
        else
            state <= s3;
            count <= x"0";
            end if;
    when s3 =>
        if count <= sec5 then
            state <= s3;
            count <= count +1;
        else
            state <= s4;
            count <= x"0";
            end if;
    when s4 =>
        if count <= sec1 then
            state <= s4;
            count <= count +1;
        else
            state <= s5;
            count <= x"0";
            end if;
    when s5 =>
        if count <= sec1 then
            state <= s5;
            count <= count +1;
        else
            state <= s0;
            count <= x"0";
            end if;
    when others =>
            state <= s0;
end case;
end if;
end process;

c2 : process (state)
begin
case state is
    when s0 => lights <= "100001";
    when s1 => lights <= "100010";
    when s2 => lights <= "100100";
    when s3 => lights <= "001100";
    when s4 => lights <= "010100";
    when s5 => lights <= "100100";
    when others => lights <= "100001";
    end case;
end process;
end traffic; 

1 个答案:

答案 0 :(得分:1)

elseif更改为elsif,以获得有效的VHDL语法。

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