Question

我的任务是编写一个简单的2到4解码器，然后显示可能的结果和波形。

我使用gEDA套件和Icarus Verilog（iVerilog）作为编译器，使用GTKWave作为波形。

这是我第一次使用Verilog编写代码或使用gEDA套件。从谷歌搜索看来，我需要遵循这个设计流程：

考虑一下你想要实现的设计。在我的例子中是一个解码器
在VHDL / Verilog中实现设计。
在VHDL / Verilog中实现测试平台。
使用iVerilog
使用testbench和.vcd转储文件使用GTKWave显示波形

testbench文件不会编译，我不知道为什么，我已经尝试了几种变体，并且我不断收到错误。任何帮助深表感谢。谢谢。

这是我的设计文件代码：

// 2 to 4 Decoder
// File Name: decoder.v

module decoder(X,Y,E,Z);
    input X,Y,E;
    output [0:3]Z;
    wire [0:3]Z;
    wire X1, Y1;

    not
        inv1(X1,X),
        inv2(Y1,Y);
    and
        and1(Z[0],X1,Y1,E),
        and2(Z[1],Y1,X,E),
        and3(Z[2],Y,X1,E),
        and4(Z[3],X,Y,E);
endmodule

这是我的测试平台代码：

module decoder_tb;
    input X,Y,E;
    output [0:3]Z;
    //wire [0:3]Z;
    //wire X1, Y1;  

    // should create .vcd dump file for GTKWave
    initial
        begin
            $dumpfile("decoder.vcd");
            $dumpvars();    
        end

    decoder decode(X,Y,E,Z);
    initial 
        begin
            $display($time,"<< Z[0]=%d   Z[1]=%d   Z[2]=%d   Z[3]=%d >>", Z[0] , Z[1] , Z[2] , Z[3] );  
        end 

    initial 
        begin 
         #0
         X = 0; Y = 0; E = 1; 
         #5 
         X = 0; Y = 1; E = 1;
         #10 
         X = 1; Y = 0; E = 1;
         #15 
         X = 1; Y = 1; E = 1;
        end 
endmodule

我正在使用的终端中的命令是：

iverilog -o decoder.vvp decoder.v decoder_tb.v
gtkwave decoder.vcd

编辑：这是确切的错误消息

aj@aj:~/verilogCode$ iverilog -o decoder.vvp decoder.v decoder_tb.v
decoder_tb.v:26: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : X is declared here as wire.
decoder_tb.v:26: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : Y is declared here as wire.
decoder_tb.v:26: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : E is declared here as wire.
decoder_tb.v:28: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : X is declared here as wire.
decoder_tb.v:28: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : Y is declared here as wire.
decoder_tb.v:28: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : E is declared here as wire.
decoder_tb.v:30: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : X is declared here as wire.
decoder_tb.v:30: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : Y is declared here as wire.
decoder_tb.v:30: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : E is declared here as wire.
decoder_tb.v:32: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : X is declared here as wire.
decoder_tb.v:32: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : Y is declared here as wire.
decoder_tb.v:32: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6:      : E is declared here as wire.
12 error(s) during elaboration.

Answer 1

在您的测试平台中，将input更改为reg，将output更改为wire。这为我修复了编译错误（虽然，我没有使用gEDA或iVerilog）：

module decoder_tb;
    reg X,Y,E;
    wire [0:3]Z;

使用gEDA和iVerilog的Verilog测试平台代码

1 个答案: