Question

我正在尝试在Post-Route模拟中运行我的项目。行为模拟工作正常，我希望它能在Spartan 3E Starter板上运行。它还能够在实现中生成编程文件。

使用ISE 14.7

我得到的错误是：

Process "Generate Post-Place & Route Simulation Model" completed successfully

Started : "Simulate Post-Place & Route HDL Model".

Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o /home/alex/projects/ece369/datapath/PostRoute_tb_isim_par.exe -prj /home/alex/projects/ece369/datapath/PostRoute_tb_par.prj work.PostRoute_tb work.glbl {}
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o /home/alex/projects/ece369/datapath/PostRoute_tb_isim_par.exe -prj /home/alex/projects/ece369/datapath/PostRoute_tb_par.prj work.PostRoute_tb work.glbl 
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Analyzing Verilog file "/home/alex/projects/ece369/datapath/src/PostRoute_tb.v" into library work
ERROR:Simulator:702 - Can not find design unit work.glbl in library work located at isim/work

在“设计选项卡”中，它将ClockDivider和DATAPATH_TEST显示为“？”。当我将关联从'all'设置为'simulation'时，文件会出现，但是我收到有关“未指定顶层模块”的错误

从谷歌搜索，我尝试了“清理项目文件”，并重新创建项目。我也尝试从/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/获取glbl.v并将其放入，但我不知道如何处理它。

我的测试平台：

`timescale 1ns / 1ps

module PostRoute_tb();
    reg              Clk, Rst, Rst_t;
    wire             Clk_slow;
    wire    [31:0]   out_0, out_1;
    reg     [31:0]   ii;

   TopClkDiv #(25) ClockDivider(
       .Clk(Clk),
       .Rst(Rst_t),
       .ClkOut(Clk_slow)    
   );

    Datapath DATAPATH_TEST(
        .Clk(Clk_slow), 
        .Rst(Rst),
        .Rst_t(Rst_t),
        .out_0(out_0),
        .out_1(out_1)
    );

    always begin
        Clk <= 0;
        #250;
        Clk <= 1;
        #250;
    end
    initial begin
        Rst <= 1;
        Rst_t <= 1;
        ii <= 0;
        #222;
        Rst <= 0;
        Rst_t <= 0;

        while (ii < 50000) begin
            @(posedge Clk_slow)
            ii = ii + 1;
        end
    end

endmodule

Answer 1

我有同样的错误

＆＃34;错误：模拟器：702 - 找不到设计单元work.glbl ...＆＃34;。

在我的案例中，我将旧的ISE 14.1项目移至PlanAhead 14.7。我的问题和解决方案是删除项目设置中的verilog_define={GLBL} - ＆gt;模拟 - ＆gt; ＆＃34; Verilog选项：＆＃34;。复选框＆＃34;加载glbl＆＃34;检查。原因是一些模拟verilog代码被封装在＆＃34; ifndef GLBL＆＃34;中。您可以通过在PlanAhead安装目录中执行"find . -type f -name "*.v" | xargs grep 'def GLBL' -sl"来找到它。

错误：模拟器：702 - 在ISim中尝试Post-Route时找不到设计单元work.glbl ....

1 个答案: