Question

我在VHDL中实现32位ALU。我发现了一个错误。我无法理解为什么我会这样做.. 是的无法更新＆＃39; in＆＃39;对象out_alu

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 ----==== Entity of AlU with input and Output 
 entity AlU is  Port (
   A : in  STD_LOGIC_VECTOR (31 downto 0);       ---== A input   Vector with 32 Bit 
   B : in  STD_LOGIC_VECTOR (31 downto 0);       ---== B input   Vector with 32 Bit 
   S : in  STD_LOGIC_VECTOR (2 downto 0) ;       ---== S select  Input Vector 3 bit for operation  
   out_AlU : in  STD_LOGIC_VECTOR (31 downto 0));---== Output of AlU 32 
 end AlU;

 architecture Behavioral of AlU is
 begin

 Select_for_operation: Process (S)   ---= Deffierent  Process for AlU with the     selection of S
                  begin
                                Case S is  
                                when     "000" =>  
                                          out_AlU <=A xor  B ;
                                when   "001"=> 
                                          out_AlU <=A Xnor B ;
                                when   "100"=> 
                                          out_AlU <=A  or  B ; 
                                when   "101"=> 
                                         out_AlU  <=A  nor B ;
                                when   "110"=> 
                                         out_AlU  <=A  and B ;
                                when    others => 
                                                    NULL ;      
                                end case ;
                        end Process ;
 end Behavioral;

Answer 1

您的信号out_ALU被声明为您实体的输入。这就是为什么你不能给它分配信号的原因（只读它就是这样说）。

将其更改为out并且可能会编译：

 entity AlU is  Port (
   A : in  STD_LOGIC_VECTOR (31 downto 0);       ---== A input   Vector with 32 Bit 
   B : in  STD_LOGIC_VECTOR (31 downto 0);       ---== B input   Vector with 32 Bit 
   S : in  STD_LOGIC_VECTOR (2 downto 0) ;       ---== S select  Input Vector 3 bit for operation  
   out_AlU : out  STD_LOGIC_VECTOR (31 downto 0));---== Output of AlU 32 
 end AlU;

在VHDL中实现32位ALU

1 个答案: