Question

我在将std_logic_vector转换为整数时遇到以下错误。我已经用Google搜索问题来修复它，但我找不到答案。请帮帮我。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity packet_size is
 generic(
   fifo_MaxDepth:integer range 0 to 256:=16
  );
port(
 fifo_tlast:in std_logic_vector(fifo_MaxDepth -1 downto 0);
 depth:in std_logic_vector(fifo_MaxDepth -1 downto 0);
 rd_ptr,wr_ptr:in integer range 0 to fifo_MaxDepth - 1;
 pckt_size:out integer range 0 to fifo_MaxDepth
   );
 end packet_size;

 architecture Behavioral of packet_size is
   signal temp:integer range 0 to 256:=0;
   variable finish_flag:bit:='0';
   variable PacketSize_temp:integer range 0 to fifo_MaxDepth;
   begin
    process (fifo_tlast,rd_ptr,wr_ptr) is
   begin
    temp<=to_integer(unsigned(depth)); --THE CONVERT STATEMENT IS HERE
     for i in rd_ptr to temp loop
        if(finish_flag='0') then
        PacketSize_temp:=PacketSize_temp + 1;
        if(fifo_tlast(i)='1') then
          finish_flag:='1';
        end if;
        end if;
     end loop;
     end process;

  end Behavioral;

我的错误是（第53行引用转换语句）

    ERROR:HDLCompiler:607 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 53: Multiple declarations of unsigned included via multiple use clauses; none are made directly visible
    ERROR:HDLCompiler:432 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 53: Formal <arg> has no actual or default value.
    ERROR:HDLCompiler:541 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 53: Type integer is not an array type and cannot be indexed.
    ERROR:HDLCompiler:854 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 45: Unit <behavioral> ignored due to previous errors.

Answer 1

您正在使用std_logic_arith 和 numeric_std。您只需要使用numeric_std，这是第一个错误（作为一般规则，在查看后续错误之前尝试解决产生的第一个错误）。修复此问题后，您会遇到另一个错误，即架构声明区域中的变量声明;变量不能在这里声明。

解决了这些问题后，您的代码至少会编译：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity packet_size is
  generic (
    fifo_MaxDepth : integer range 0 to 256 := 16
  );
  port (
    fifo_tlast : in std_logic_vector(fifo_MaxDepth -1 downto 0);
    depth : in std_logic_vector(fifo_MaxDepth -1 downto 0);
    rd_ptr, wr_ptr: in integer range 0 to fifo_MaxDepth - 1;
    pckt_size : out integer range 0 to fifo_MaxDepth
  );
end packet_size;

architecture Behavioral of packet_size is
  signal temp : integer range 0 to 256 := 0;
  signal finish_flag : bit := '0';
  signal PacketSize_temp : integer range 0 to fifo_MaxDepth;
begin

  process (fifo_tlast, rd_ptr, wr_ptr) is
  begin
    temp <= to_integer(unsigned(depth));
    for i in rd_ptr to temp loop
      if (finish_flag = '0') then
        PacketSize_temp <= PacketSize_temp + 1;
        if (fifo_tlast(i) = '1') then
          finish_flag <= '1';
        end if;
      end if;
    end loop;
  end process;

end Behavioral;

我还在作业中添加了空格，通常是为了提高可读性。

HDLCompiler：将std_logic_vector转换为整数时出错432

1 个答案: