Question

我在verilog if-else语句中遇到问题。我试图制作一个数字时钟和我的tick_counter模块代码。我指着带注释行的错误行。我找不到解决办法，请帮助我。

module tick_counter(
input clk,
input tick_in,
output [3:0] ssd_2, ssd_4,
output [2:0] ssd_3
);
reg [5:0] count1, count_next1;
reg [2:0] count2, count_next2;
reg [3:0] count3, count4, count_next3, count_next4;

always@(posedge clk)
    begin
        count1 <= count_next1;
        count2 <= count_next2;
        count3 <= count_next3;
        count4 <= count_next4;
    end
//next state logic
always@*
    begin
        if(tick_in)
            begin
                if(count1==6'b111100)               //second counter
                    begin
                        count_next1 = 6'b0;
                        count_next2 = count2 + 1'b1;
                    end
                else
                    count_next1 = count1 + 1'b1;
                if(count2==4'b1001)                 //minutes counter of LSB digit
                    begin
                        count_next2 = 4'b0000;
                        count_next3 = count3 + 1'b1;
                    end
                else
                    count_next2 = count2 + 1'b1;
                if(count3==3'b101)                  //minutes counter of MSB digit
                    begin
                        count_next3 = 3'b000;
                        count_next4 = count4 + 1'b1;
                    end
                else
                    count_next3 = count3 + 1'b1;
                if(count4==4'b1001)                 //counter hour
                    begin                 
                        count_next4 = 4'b0000;
                    end
                else
                    count_next4 = count4 + 1'b1;
        else                                        //---THE POINT OF ERROR------
            begin
                count_next1 = count1;
                count_next2 = count2;
                count_next3 = count3;
                count_next4 = count4;
            end
    end
end


    assign ssd_2 = count2;
    assign ssd_3 = count3;
    assign ssd_4 = count4;

endmodule

Answer 1

当然endmodule缺失了。但这可能是你的错字错误。

大型设计极大地鼓励了适当的缩进。在缩进代码后，我发现在end条件的{/ strong> else部分之后，// counter hour 丢失了一个if 。因此，您的主要end条件end被错误放置。只需在指定位置添加end，然后从始终阻止的最后一个中删除一个{% url 'polls:detail' question_id %}。

请进行适当的缩进，以便调试变得容易。

verilog if-else错误消息

1 个答案: