VHDL仿真不显示波形

Question

我用VHDL编写代码并使用Active HDL Student版本使用测试平台编译和模拟代码。当我模拟500ns时，信号会发生变化，但波形上的信号会粘在U上而不显示任何内容。我似乎无法找到造成这个问题的原因。

这是我的实体代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity idexreg is
    port(
    rst_bar : in std_logic;
    clk : in std_logic;
    immediate_in : in std_logic_vector(63 downto 0);
    reg0_in : in std_logic_vector(63 downto 0);
    reg1_in : in std_logic_vector(63 downto 0);
    instruction_in : in std_logic_vector(3 downto 0);
    pc_in : in std_logic_vector(3 downto 0);
    immediate_out : out std_logic_vector(63 downto 0); 
    reg0_out : out std_logic_vector(63 downto 0);  
    reg1_out : out std_logic_vector(63 downto 0); 
    instruction_out : out  std_logic_vector(3 downto 0);
    pc_out : out std_logic_vector(3 downto 0)
    );
end idexreg;       

architecture idexreg_arch of idexreg is 
begin
    arch: process(clk, rst_bar)
    begin
        if rst_bar = '0' then
            immediate_out <= std_logic_vector(x"0000000000000000");
            reg0_out <= std_logic_vector(x"0000000000000000");
            reg1_out <= std_logic_vector(x"0000000000000000");
            instruction_out <= std_logic_vector(x"0");
            pc_out <= std_logic_vector(x"0");       
        elsif falling_edge(clk) then
            immediate_out <= immediate_in;
            reg0_out <= reg0_in;
            reg1_out <= reg1_in;
            instruction_out <= instruction_in;
            pc_out <= pc_in;
        end if;
    end process;
end idexreg_arch;

这是测试平台的代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; 
use ieee.std_logic_arith.all;

entity idexreg_tb is
end idexreg_tb;

architecture test of idexreg_tb is 
--input signals
signal rst_bar : std_logic;
signal clk: std_logic;
signal immediate_in  : std_logic_vector(63 downto 0);
signal reg0_in : std_logic_vector(63 downto 0);
signal reg1_in : std_logic_vector(63 downto 0);
signal instruction_in : std_logic_vector(3 downto 0);
signal pc_in : std_logic_vector(3 downto 0); 

--output signals
signal immediate_out  : std_logic_vector(63 downto 0);
signal reg0_out : std_logic_vector(63 downto 0);
signal reg1_out : std_logic_vector(63 downto 0);
signal instruction_out : std_logic_vector(3 downto 0);
signal pc_out : std_logic_vector(3 downto 0); 

-- boolean to signify end of simulation
signal end_sim : boolean := false; 

constant period : time := 50ns;

begin

UUT: entity idexreg 
    port map(
    rst_bar => rst_bar,
    clk => clk,
    immediate_in => immediate_in,
    reg0_in => reg0_in,
    reg1_in => reg1_in,
    instruction_in => instruction_in,
    pc_in => pc_in,
    immediate_out => immediate_out,
    reg0_out => reg0_out,
    reg1_out => reg1_out,
    instruction_out => instruction_out,
    pc_out => pc_out);


-- Generate the Clock signal
clk_gen: process 
begin
clk <= '0';
loop
    wait for period/2;
    clk <= not clk;
    exit when end_sim = true;
end loop;
wait;
end process;

stim: process
begin
    -- reset the register file first
    rst_bar <= '0';
    wait for 100ns;
    rst_bar <= '1';


    --Test 1
    immediate_in <= std_logic_vector(x"AAAAAAAAAAAAAAAA");
    reg0_in <=  std_logic_vector(x"AAAAAAAAAAAAAAAA");
    reg1_in <=  std_logic_vector(x"AAAAAAAAAAAAAAAA");
    instruction_in <= std_logic_vector(x"A");
    pc_in <= std_logic_vector(x"1");
    wait for 10ns;
    --Test 2
    immediate_in <= std_logic_vector(x"BBBBBBBBBBBBBBBB");
    reg0_in <=  std_logic_vector(x"BBBBBBBBBBBBBBBB");
    reg1_in <=  std_logic_vector(x"BBBBBBBBBBBBBBBB");
    instruction_in <= std_logic_vector(x"B");
    pc_in <= std_logic_vector(x"2"); 
    wait for 30ns;
    --Test 3
    immediate_in <= std_logic_vector(x"CCCCCCCCCCCCCCCC");
    reg0_in <=  std_logic_vector(x"CCCCCCCCCCCCCCCC");
    reg1_in <=  std_logic_vector(x"CCCCCCCCCCCCCCCC");
    instruction_in <= std_logic_vector(x"C");
    pc_in <= std_logic_vector(x"3"); 
    end_sim <= true;

    wait;
end process;   

end test;

非常感谢任何帮助！