UVM - 错误 - :接近"(&#34 ;:语法错误,意外'(',期待IDENTIFIER或' ='

时间:2016-12-14 14:10:29

标签: macros system-verilog uvm

我创建自己的宏文件:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg)\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)

`define add_rand(mem_type, mem) \
  begin \
   case (mem_type) \
     "int": add_rand_int(mem); \
     "bit": add_rand_bit(mem); \
     default: `uvm_fatal("FATAL ERROR", "type is not supported") \
    endcase\
  end

`endif  //MY_MACROS_SV

我收到以下错误:

** at .. \ sv \ tx_transaction.sv(21):near"(&#34 ;:语法错误,意外'(',期待IDENTIFIER或' ='

tx_transaction.sv中的第21行:

  add_rand_macro();

add_rand是一个在base_transaction中定义的函数(tx_transaction扩展它):

class base_transaction extends uvm_sequence_item();

   int rand_int_list [];   
   bit rand_bit_list [];


   bit [31:0] data [$];

   //add to list functions
   function void add_rand_int(int mem);
      rand_int_list.push_back(mem);      
   endfunction: add_rand_int
   ......
endclass: base_transaction

tx_transaction的代码:

class tx_transaction extends base_transaction;
   bit [15:0]  data_xi;
   bit [15:0]  data_xq;
   int mem_int;  //TODO- delete

   //uvm_object_utils\
   `uvm_object_utils(tx_transaction)

   //constructor
   function new(string name = "tx_transaction");
      super.new(name);
   endfunction: new

   function void add_rand_macro();
      `add_rand("int", mem_int)
   endfunction: add_rand_macro

   add_rand_macro();

   //TODO - DELETE
   function void foo();
      $display("rand mem int: %d", mem_int);
   endfunction: foo

endclass: tx_transaction

1 个答案:

答案 0 :(得分:1)

由于宏扩展为case语句,因此必须从类中的函数内部调用它:

function ...

    ...
   `add_rand("int", mem_int)   
    ...

endfunction

更新:确保使用分号结束function声明:

function void add_rand_macro();
    `add_rand("int", mem_int)
endfunction

更新:你不能在课堂上调用add_rand_macro函数;它必须在另一个函数内调用。

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