分层块＆lt;＆gt;在块＆lt;＆gt;中未连接。它将从设计中删除

Question

我是穆罕默德，我正在尝试编写一个带有异步复位的BCD计数器，该计数器连接到一个按钮。它也可以获得8位输入。 我的所有代码和模块都工作正常，除了Debouncer，我用它来去除按钮。模块本身工作正常，但当我实例化它时 ＆＃34;分块块在块中未连接。    它将从设计中删除。＆＃34; 出现！ 这是我的主要代码：

module BCD_main(
    input clk,
    input reset,
     input [7:0] inp,
    output wire [6:0] main_out0,
    output wire [6:0] main_out1
    );

    reg [7:0] in ;
    reg [7:0] count ;
    reg [3:0] out0 ;
    reg [3:0] out1 ;
    wire clk_main ;
    wire reset_in ;
    assign reset_in = reset ;
    wire reset_out ;
    wire clk_en ;
    assign clk_main = clk ;

    initial begin
    out0 <= 0 ;
    in <= 0 ;
    count <= 0 ;
    out1 <= 0 ;
    end

    Enable count_enable (
        .En_clk(clk_main),
        .CE(clk_en)
    );


     Debouncer debounce (
    .clk(clk), 
    .pb_in(reset_in), 
    .pb_out(reset_out)
    );

    always @(inp) count <= 0 ;

    always @(posedge clk or negedge reset_out)
        begin
        if (~reset_out) begin
            out1 <= 0 ;
            out0 <= 0 ;
            in <= 0 ;
        end         
        else if (clk_en) begin
        count <= count + 1 ;
        in <= inp + count ;
        if ( in <= 9) begin
            out1 <= 0 ;
            out0 <= in ;
        end
        else if(in > 9 && in <= 19) begin
            out1 <= 1 ;
            out0 <= in - 10 ;
        end
        else if( in > 19 && in <= 29) begin
            out1 <= 2 ;
            out0 <= in - 20 ;
        end
        else if( in > 29 && in <= 39) begin
            out1 <= 3 ;
            out0 <= in - 30 ;
        end
        else if( in > 39 && in <= 49) begin
            out1 <= 4 ;
            out0 <= in - 40 ;
        end
        else if( in > 49 && in <= 59) begin
            out1 <= 5 ;
            out0 <= in - 50 ;
        end
        else if( in > 59 && in <= 69) begin
            out1 <= 6 ;
            out0 <= in - 60 ;
        end
        else if( in > 69 && in <= 79) begin
            out1 <= 7 ;
            out0 <= in - 70 ;
        end
        else if( in > 79 && in <= 89) begin
            out1 <= 8 ;
            out0 <= in - 80 ;
        end
        else if( in > 89 && in <= 99) begin
            out1 <= 9 ;
            out0 <= in - 90 ;
        end
        else if ( in > 99) begin
            out1 <= 0 ;
            out0 <= 0 ;
        end
        end


        end 

        DipSWtoSS SevSegDec(
            .DpSw_1(out0),
            .DpSw_2(out1),
            .SevSeg_1(main_out0),
            .SevSeg_2(main_out1)

        );




endmodule

这是debouncer模块：

module Debouncer(
     input clk ,
    input pb_in,
    output reg pb_out
    );

     reg [12:0] count13 ;

     initial begin 
     pb_out <= 1 ;
     count13 <= 0 ;
     end

     always @(pb_in) count13 <= 0 ;


     always @(posedge clk) begin
            count13 <= count13 + 1 ;
            if (count13 == 13'd8000) 
                pb_out <= pb_in ;
            else 
                pb_out <= 1 ;

     end
endmodule