Question

我试图访问Cortex-M3的SysTick定时器，所以我要切换到特权模式。我这样做是为了

/* Active previlige mode */
asm ("mov r0, #0x0");
asm ("msr control, r0");
asm ("ISB");

但它无法正常工作，因为我无法写入SYST_CSR寄存器。如果是，则执行此操作需要任何异常条目，如何？

Answer 1

您无法直接从用户模式将模式提升为特权（您可以直接从特权模式更改为用户模式）。您必须通过SVC呼叫（主管呼叫）来执行此操作。

如果在C中执行此操作，如何引发SVC调用将取决于您的编译器，但在汇编程序中，您可以使用asm("svc, #1");

#1可以是任意数字。这可供SVC处理程序使用。如果您只想将SVC处理程序用于此目的，那么您不需要解码处理程序中的数字，只需使用上面的程序集来提高权限即可。但是，如果您想将SVC用于多个目的，那么您需要对数字进行解码，以便＃1用于提升权限，＃2用于执行其他操作等。这里要知道的主要事项是SVC号码将在您拨打电话时使用的堆栈上（msp或psp）。如果你只使用一个堆栈那么它就更容易了。您必须在用户指南中查找堆栈框架。

所以你需要实现一个SVC处理程序。你应该在网上找到一些例子。 “ARM Cortex-M3和Cortex M4权威指南”一书中有一个很好的例子。

Answer 2

Janathan Valvano在http://users.ece.utexas.edu/~valvano/arm/#Timer

拥有SysTick计时器代码示例和其他内容

; SysTickInts.s
; Runs on LM4F120/TM4C123
; Use the SysTick timer to request interrupts at a particular period.
; Daniel Valvano
; September 11, 2013

;  This example accompanies the book
;   "Embedded Systems: Introduction to ARM Cortex M Microcontrollers"
;   ISBN: 978-1469998749, Jonathan Valvano, copyright (c) 2013
;   Volume 1, Program 9.7

;   "Embedded Systems: Real Time Interfacing to ARM Cortex M Microcontrollers",
;   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013
;   Volume 2, Program 5.12, section 5.7
;
;Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
;   You may use, edit, run or distribute this file
;   as long as the above copyright notice remains
;THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
;OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
;MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
;VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
;OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
;For more information about my classes, my research, and my books, see
;http://users.ece.utexas.edu/~valvano/

NVIC_ST_CTRL_R        EQU 0xE000E010
NVIC_ST_RELOAD_R      EQU 0xE000E014
NVIC_ST_CURRENT_R     EQU 0xE000E018
NVIC_ST_CTRL_COUNT    EQU 0x00010000  ; Count flag
NVIC_ST_CTRL_CLK_SRC  EQU 0x00000004  ; Clock Source
NVIC_ST_CTRL_INTEN    EQU 0x00000002  ; Interrupt enable
NVIC_ST_CTRL_ENABLE   EQU 0x00000001  ; Counter mode
NVIC_ST_RELOAD_M      EQU 0x00FFFFFF  ; Counter load value
NVIC_SYS_PRI3_R       EQU 0xE000ED20  ; Sys. Handlers 12 to 15 Priority

        AREA    |.text|, CODE, READONLY, ALIGN=2
        THUMB
        EXPORT   SysTick_Init

; **************SysTick_Init*********************
; Initialize SysTick periodic interrupts, priority 2
; Input: R0  interrupt period
;        Units of period are 1/clockfreq
;        Maximum is 2^24-1
;        Minimum is determined by length of ISR
; Output: none
; Modifies: R0, R1, R2, R3
SysTick_Init
    ; start critical section
    MRS    R3, PRIMASK              ; save old status
    CPSID  I                        ; mask all (except faults)
    ; disable SysTick during setup
    LDR R1, =NVIC_ST_CTRL_R         ; R1 = &NVIC_ST_CTRL_R (pointer)
    MOV R2, #0
    STR R2, [R1]                    ; disable SysTick
    ; maximum reload value
    LDR R1, =NVIC_ST_RELOAD_R       ; R1 = &NVIC_ST_RELOAD_R (pointer)
    SUB R0, R0, #1                  ; counts down from RELOAD to 0
    STR R0, [R1]                    ; establish interrupt period
    ; any write to current clears it
    LDR R1, =NVIC_ST_CURRENT_R      ; R1 = &NVIC_ST_CURRENT_R (pointer)
    STR R2, [R1]                    ; writing to counter clears it
    ; set NVIC system interrupt 15 to priority 2
    LDR R1, =NVIC_SYS_PRI3_R        ; R1 = &NVIC_SYS_PRI3_R (pointer)
    LDR R2, [R1]                    ; friendly access
    AND R2, R2, #0x00FFFFFF         ; R2 = R2&0x00FFFFFF (clear interrupt 15 priority)
    ORR R2, R2, #0x40000000         ; R2 = R2|0x40000000 (interrupt 15 priority is in bits 31-29)
    STR R2, [R1]                    ; set SysTick to priority 2
    ; enable SysTick with core clock
    LDR R1, =NVIC_ST_CTRL_R         ; R1 = &NVIC_ST_CTRL_R
; ENABLE SysTick (bit 0), INTEN enable interrupts (bit 1), and CLK_SRC (bit 2) is internal
    MOV R2, #(NVIC_ST_CTRL_ENABLE+NVIC_ST_CTRL_INTEN+NVIC_ST_CTRL_CLK_SRC)
    STR R2, [R1]                    ; store a 7 to NVIC_ST_CTRL_R
    ; end critical section
    MSR    PRIMASK, R3              ; restore old status
    BX  LR                          ; return

    ALIGN                           ; make sure the end of this section is aligned
    END                             ; end of file

切换到cortex-m3中的特权模式

2 个答案: