Question

现在我试图按照下面的方式实现内存模型，

但是我收到了警告信息

assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};
                                       |
ncelab: *W,BIGWIX (./sram.v,16|39): Memory index truncation.  
    Mem[Address] = Data;
              |
ncelab: *W,BIGWIX (./sram.v,20|14): Memory index truncation.

完成

// RAM Model
//


module sram (Address, Data, CS, WE, OE);

parameter AddressSize = 2592;
parameter WordSize = 32;

input [AddressSize-1:0] Address;
inout [WordSize-1:0] Data;
input CS, WE, OE;

reg [WordSize-1:0] Mem [0:(1<<AddressSize)-1];

assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};

always @(CS or WE)
  if (!CS && !WE)
    Mem[Address] = Data;

always @(WE or OE)
  if (!WE && !OE)
    $display("Operational error in RamChip: OE and WE both active");

endmodule

＆＃34;内存索引截断＆＃34;意思？

Answer 1

您可以使用nchelp获取有关任何Cadence Incisive警告的详细帮助：

nchelp ncelab BIGWIX
ncelab/BIGWIX =
    A memory is being indexed. The index expression has a width
    greater than a machine word, which is typically 32 bits.
    Only 32 bits are used. This truncation may result in
    undesired behavior.

如评论中所述，您可能不希望地址输入信号为2592位宽或您的存储器具有（1 <＆lt;＆lt; 2592）位置。

什么＆＃34;内存索引截断＆＃34;在verilog中意味着什么？

1 个答案: