Question

我是vhdl的新手并尝试使用5条选择线为多路复用器制作测试台，但它给我带来了错误（代码很长，所以我只是复制了包含错误的部分）

代码：

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    use ieee.numeric_std.all;
    entity Mux_4_to_1_tb is
    end Mux_4_to_1_tb;

    architecture tb of Mux_4_to_1_tb is

    component Mux_4_to_1 is
      port( clock : in std_logic;
        D0, D1, D2, D3 : in std_logic; -- the data lines D0=A0 D1=A1 D2=B0 D3=B1
            S0, S1, S2, S3, S4  : in std_logic; -- the selector switches
            F : out std_logic_vector(2 downto 0)
        );-- the output
    end component;
    constant clockperiod : time := 20 ns;
    signal D0, D1, D2, D3, S0, S1 , S2, S3, S4  , F : std_logic;
    signal selectors : std_logic_vector(4 downto 0);

    begin
    mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );

    --Concurrent processes
    process
    begin   

      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '1'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      end process;

      process(S4, S3, S2, S1, S0)
      begin
       selectors <= S0&S1&S2&S3&S4;
        end process;

       process
       begin

      --The "assert" keyword allows you to test certain 
      --conditions. In other words, the point of assertion is
      --to allow you to inspect what you expect.

      --Two test cases are presented here. Feel free 
      --to add your own cases.

       --TEST 1
         D0 <= '0';
        D1 <= '1';
        D2 <= '0';
        D3 <= '1';
        wait for clockperiod;
        case selectors is
         when "00000" =>
           assert(F => "000") report "Error 1: 00000" severity error;

错误：

**错误：E：\ OneDrive \ Engineering \ Digital Circuit Design \ TestBench.vhd（70）:( vcom-1581）中缀运算符'='没有可行条目。
<<错误：E： \ OneDrive \ Engineering \ Digital Circuit Design \ TestBench.vhd（70）：键入错误解析中缀表达式“=”作为类型std.STANDARD.BOOLEAN。

错误将我指向断言字的行。

此外，我在代码末尾出现此错误

代码：

 when others =>
     assert true;
  end case;
end process;
end tb;

错误：

**错误：E：\ OneDrive \ Engineering \ Digital Circuit Design \ TestBench.vhd（229）：VHDL编译器退出

错误将我指向最后一行。

Answer 1

在没有透露Mux_4_to_1内容的情况下，您未提供有关此测试平台应如何运作的任何信息。

断言语句条件有两个问题：

assert(F => "000")

F被声明为类型std_logic，它不是数组类型，不能与字符串值（具有可由上下文确定的数组类型）进行比较。关系运算符也应该是>=而不是=>，读作＆＃39;大于或等于＆＃39;。 =>是用于关联的分隔符。

更改关系运算符并更改F的声明：

signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 :  std_logic; --  , F : std_logic;
signal F:   std_logic_vector (2 downto 0);

生成错误，告知我们F无法与S4相关联，告诉我们您有参数列表错误。你没有足够的参数。不提供输出关联并不是错误，这就是之前没有注意到的原因，尽管读者可能会假设您更改了F的声明以先验地消除该错误

为时钟添加信号声明：

constant clockperiod : time := 20 ns;
signal clock:   std_logic;

并添加关联：

begin
-- mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );
mapping: 
    Mux_4_to_1 
        port map (
            clock => clock,
            D0 => D0,
            D1 => D1,
            D2 => D2,
            D3 => D3, 
            S0 => S0,
            S1 => S1,
            S2 => S2,
            S3 => S3,
            S4 => S4, 
            F => F
        );

允许您的代码进行分析（通过将找到的代码与其他选项连接到VHDL代码的末尾，您不提供Minimal, Complete and Verifiable example）。

注意：

clock未在变更说明中显示，如果测试需要，则应由测试平台驱动。
正式关联显示在Mux_4_to_1的即时消息的端口映射中，它允许您查看缺少或错误的正式到实际端口关联。
周围条件的多余括号可能会掩盖错误。如果它们包含的表达在没有它们的情况下合法，它们才是合法的它可以更改您看到的错误消息。缺少适当的关系运算符会导致语法错误。

VHDL多路复用器测试平台错误

1 个答案: