Question

我知道在SO上已经遇到过几次这个错误，但作为一个初学者，我仍然无法看到如何在我自己的代码中解决这个错误。错误和代码都打印在下面，感谢任何人的意见。

错误（10818）：无法在5bit_PHreg_vhdl.vhd（21）推断计数[0]的寄存器，因为它不会在时钟边缘之外保持其值

对'count'的每一位重复该错误，并引用代码中注明的行。

ARCHITECTURE behavioral OF 5bit_PHreg_vhdl IS
SIGNAL count    :   STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN
    PROCESS(reset, clk, SHR_EN)
        BEGIN
-- Check if asynchronous reset is 0
        IF reset = '0' THEN --ERROR OCCURS HERE
                count <= "00000";
-- Check if rising edge
        ELSIF (clk'EVENT AND clk = '1') THEN
                IF LD_EN = '1' THEN
                    count <= FA_in;
                END IF;
-- Check if SHR_EN is active
        ELSIF (SHR_EN = '1') THEN
                count(4) <= c_in;
                count(3) <= count(4);
                count(2) <= count(3);
                count(1) <= count(2);
                count(0) <= count(1);
                c_out <= count(0);
        END IF;
    END PROCESS;
    PH_reg_out <= count;
END behavioral;

Answer 1

5bit_PHreg_vhdl超出了复位和时钟边缘条件，它的形式无法识别为合成。

如果已注册，则将其移至上一个内容中。从过程敏感性列表中删除SHR_EN。

同样在VHDL中，名称不能以数字开头，library ieee; use ieee.std_logic_1164.all; entity PH_reg_5_bit is port ( reset: in std_logic; clk: in std_logic; LD_EN: in std_logic; SHR_EN: in std_logic; FA_in: in std_logic_vector (4 downto 0); c_in: in std_logic; c_out: out std_logic; PH_reg_out: out std_logic_vector (4 downto 0) ); end entity; ARCHITECTURE behavioral OF PH_reg_5_bit IS SIGNAL count : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN PROCESS (reset, clk) -- , SHR_EN) BEGIN -- Check if asynchronous reset is 0 IF reset = '0' THEN --ERROR OCCURS HERE count <= "00000"; -- Check if rising edge ELSIF (clk'EVENT AND clk = '1') THEN IF LD_EN = '1' THEN count <= FA_in; -- Check if SHR_EN is active ELSIF (SHR_EN = '1') THEN count(4) <= c_in; count(3) <= count(4); count(2) <= count(3); count(1) <= count(2); count(0) <= count(1); END IF; -- -- Check if SHR_EN is active -- ELSIF (SHR_EN = '1') THEN -- count(4) <= c_in; -- count(3) <= count(4); -- count(2) <= count(3); -- count(1) <= count(2); -- count(0) <= count(1); -- c_out <= count(0); END IF; END PROCESS; c_out <= count(0); -- c_out not separately registered PH_reg_out <= count; END behavioral;作为实体名称无效。

修复这些并填写缺少的实体声明：

c_out

并且您的代码分析成功。

实体名称很好地表明您没有模拟您的设计。

注意条件的顺序意味着加载优先于转移。

我怀疑os.path.abspath()不应该注册，允许使用c_in和c_out将移位寄存器实例连接到更大的移位寄存器中。这意味着它的赋值应该在包含时钟边沿事件的if语句之外，它可以在另一个输出引脚分配旁边。

VHDL代码错误：“错误（10818）：无法推断<location>处的<name>的寄存器，因为它没有在时钟边缘之外保持其值”

1 个答案: