在将fifo代码实例化到我的顶层模块时，我遇到了另一个难题。我想从我的串行端口（接收子系统）存储一些数据集“欢迎来到FPGA的世界”，然后我想要检索它，当按下fpga板上的按钮或FIFO已满时。我写了我的fifo代码和串行通信代码。 Idea是从键盘发送的数据 - ＆gt;接收子系统 - ＆gt; FIFO - ＆gt;传输子系统 - ＆gt;超级终端。我目前正在使用8位宽的FIFO，并说28深只是为了存储一些小数据。在这方面请帮助我如何实现它。我有来自接收器的字节保存在register_save中。 fifo code
inst_bit8_recieve_unit : entity work.byte_recieve_8N1
port map ( ck => ck,
reset => reset,
new_byte_in_buffer => new_byte_in_buffer,
byte_read_from_buffer => byte_read_from_buffer,
recieve_buffer => register_save,
JA_2 => JA(2));
---------------------FIFO instantiate-------------------------------
inst_of_fifo_Recieve_unit : entity work.fifo
generic map (B => data_bits, W => fifo_width)
port map ( ck => ck,
reset => reset,
rd => rd_rx,
wr => wr_rx,
write_data => num_recieved,
read_data => num_recieved_fifo,
empty => empty_rx,
full => full_rx );
inst_bit8_transmit_unit : entity work.byte_transmit_8N1
port map ( ck => ck,
reset => reset,
send_byte_ready => send_byte_ready,
send_byte_done => send_byte_done ,
send_buffer => num_send,
JAOUT_0 => JAOUT );
proc_send5byte: process(ck, reset, state_byte5, send_byte_done, num_send, state_button_0, num_recieved_fifo, rd_rx)
begin
if reset = '1' THEN
state_byte5 <= idle;
send_byte_ready <='0';
num_send <= "00000000" ;
else
if rising_edge(ck) then
case state_byte5 is
when idle => ---- in this, if btn(0) is high i.e pressed then only state_byte5 will go to next state
if state_button_0 = transit_pressed then
state_byte5 <= byte;
end if;
-----===============================================================
when byte =>
if (not empty_rx = '1') then
if send_byte_ready ='0' and send_byte_done = '0' then ----here if condition is satified the send_byte_ready will be set
send_byte_ready <='1'; --------- shows next byte is ready
num_send <= num_recieved_fifo;
rd_rx <='1';
end if;
end if;
if send_byte_ready = '1' and send_byte_done = '1' then --- during load state send_byte will be resets
send_byte_ready <='0';
rd_rx <= '0';
state_byte5 <= idle; ----------- go back to idle
end if;
--end if;
---===============================================================
when others =>
state_byte5 <= idle; ------------- for other cases state state _byte5 will be in idle
send_byte_ready <= '0';
rd_rx <= '0';
end case;
end if;
end if;
end process;
proc_recieving_byte : process (ck, reset, register_save, new_byte_in_buffer, full_rx, num_recieved, wr_rx)
begin
if reset = '1' then
byte_read_from_buffer <= '0';
else
if rising_edge(ck) then
if full_rx = '0' then
if new_byte_in_buffer = '1' and byte_read_from_buffer = '0' then
byte_read_from_buffer <= '1';
wr_rx <= '1';
num_recieved(7 downto 0 ) <= register_save( 7 downto 0);
end if;
end if;
if new_byte_in_buffer = '0' then
byte_read_from_buffer <= '0';
wr_rx <= '0';
end if;
--end if;
end if;
end if;
end process;
现在添加了修正后的代码似乎正常工作。当增加fifo的深度时出现问题。当深度> 2时，则缺少每第三个字节。 请帮忙，为什么我要丢失数据。
答案 0 :(得分：0)
fifo的原则是先入先出。你没有管理它。
然后数据存储，再次执行以存储另一个值。
当您想要阅读所有数据时（Fifo full /您想要的任何情况）
将读使能位设置为'1'并且每个时钟周期，您将收到一个数据。
答案 1 :(得分：-2)
--- process for recieving bytes and sent to fifo input with write enable signal------------
proc_recieving_byte : process (ck, reset, register_save, new_byte_in_buffer, full_rx, num_recieved, wr_rx)
begin
if reset = '1' then
byte_read_from_buffer <= '0';
else
if rising_edge(ck) then
if full_rx = '0' then
if new_byte_in_buffer = '1' and byte_read_from_buffer = '0' then
byte_read_from_buffer <= '1';
wr_rx <= '1';
num_recieved(7 downto 0 ) <= register_save( 7 downto 0);
else
wr_rx <= '0';
end if;
end if;
if new_byte_in_buffer = '0' then
byte_read_from_buffer <= '0';
wr_rx <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------
---- this process checks first button state and then transmission occurs from fifo untill empty------
proc_send5byte: process(ck, reset, state_byte5, send_byte_done, num_send, state_button_0, num_recieved_fifo, rd_rx)
begin
if reset = '1' THEN
state_byte5 <= idle;
send_byte_ready <='0';
num_send <= "00000000" ;
else
if rising_edge(ck) then
case state_byte5 is
when idle => ---- in this, if btn(0) is high i.e pressed then only state_byte5 will go to next state
if state_button_0 = transit_pressed then
state_byte5 <= byte;
end if;
-----===============================================================
when byte =>
if (not empty_rx = '1') then
if send_byte_ready ='0' and send_byte_done = '0' then ----here if condition is satified the send_byte_ready will be set
send_byte_ready <='1'; --------- shows next byte is ready
num_send <= num_recieved_fifo;
rd_rx <='1';
else
rd_rx <='0';
end if;
end if;
if send_byte_ready = '1' and send_byte_done = '1' then --- during load state send_byte will be resets
send_byte_ready <='0';
rd_rx <= '0';
state_byte5 <= idle; ----------- go back to idle
end if;
---===============================================================
when others =>
state_byte5 <= idle;
send_byte_ready <= '0';
rd_rx <= '0';
end case;
end if;
end if;
end process;
刚刚发现错误并按上述方法更正，效果非常好。欢迎提出改进意见。