Question

我正在学习vhdl并尝试在vivado中设计半加法器。我在下面编写了设计和测试平台的代码，并尝试模拟它但是出错了。请各位支持！我也很感激我可以从中学到的任何有用的链接。

错误记录：

    syntax error near sum [half_adder.vhd:44]

    syntax error near carry [half_adder.vhd:45]

    unit behavioral ignored due to previous errors [half_adder.vhd:41]

以下是设计代码： 的 half_adder.vhdl

   library IEEE;

   use IEEE.STD_LOGIC_1164.ALL;
   entity half_adder is
   Port ( 
       x : in STD_LOGIC;
       y : in STD_LOGIC;
       sum : out STD_LOGIC;
       carry : out STD_LOGIC
     ); 

Line 41 -- end half_adder;

architecture Behavioral of half_adder is 
Line 44 --   begin
Line 45 -- assign sum<=x xor y; 
assign carry<= x and y;

end Behavioral;

以下是测试平台代码： 的 ha_tb.vhdl

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
entity ha_tb is
end ha_tb;

 architecture Behavioral of ha_tb is
 component halfa is
 port(
      x : in STD_LOGIC;
  Line 41--    y : in STD_LOGIC;
      sum : out STD_LOGIC;
      carry : out STD_LOGIC
 Line 44--    );
 Line 45--  end component; 
 signal input1,input2: in STD_LOGIC;
 signal outputs,outputc: in STD_LOGIC;

 begin
 HA:halfa port map (x=>input1,y=>input2,sum=>outputs,carry=>outputc);
 stimulus_proc:process
 begin
x<='0';
y<='0';
wait for 20ns;
 x<='0';
   y<='1';
   wait for 20ns;
    x<='1';
      y<='0';
      wait for 20ns;
       x<='1';
         y<='1';
         wait;
  end process;

 end Behavioral;

Answer 1

使用此代码检查，分配功能，您只能在vhdl分配功能中使用Verilog不支持

library IEEE;

   use IEEE.STD_LOGIC_1164.ALL;
   entity half_adder is
   Port ( 
       x : in STD_LOGIC;
       y : in STD_LOGIC;
       sum : out STD_LOGIC;
       carry : out STD_LOGIC
     ); 

Line 41 -- end half_adder;

architecture Behavioral of half_adder is 
begin
sum<=x xor y; 
carry<= x and y;

end Behavioral;

模拟VHDL Half Adder但出现错误

1 个答案: