我正确地证实了模块，但在ISE14.7上继续得到Xst：1290警告

Question

我的顶级模块代码如下：

module top_clock(
input CLK_50,
input nCR,
input EN,
input Adj_Min,
input Adj_Hour,
output[6:0] SEG,
output[3:0] SEL,
output reg secLED
    );
wire[7:0] Hour=8'h00;
wire[7:0] Minute=8'h00;
wire[7:0] Second=8'h00;
supply1 Vdd;
wire MinL_EN,MinH_EN,Hour_EN;
wire CP_1Hz;
//============分频===============
Divider50MHz U0(.CLK_50M(CLK_50),.nCLR(nCR),.CLK_1HzOut(CP_1Hz));
defparam U0.N=25,
         U0.CLK_Freq=50000000,
            U0.OUT_Freq=1;
//==============================

//============时间计数器================

(*KEEP_HIERARCHY="TRUE"*)
counter10 S0(.Q(Second[3:0]),.CP(CP_1Hz),.nCR(nCR),.EN(EN));


(*KEEP_HIERARCHY="TRUE"*)
counter6 S1(.Q(Second[7:4]),.nCR(nCR),.EN(Second[3:0]==4'h9),.CP(CP_1Hz));

(*KEEP_HIERARCHY="TRUE"*)
counter10 M0(.Q(Minute[3:0]),.nCR(nCR),.EN(MinL_EN),.CP(CP_1Hz));


(*KEEP_HIERARCHY="TRUE"*)
counter6 M1(.Q(Minute[7:4]),.nCR(nCR),.EN(MinH_EN),.CP(CP_1Hz));

assign MinL_EN = Adj_Min? Vdd: (Second==8'h59);
assign MinH_EN = (Adj_Min&&(Minute[3:0]==4'h9))||((Minute[3:0]==4'h9)&&(Second==8'h59));


(*KEEP_HIERARCHY="TRUE"*)
counter24 H0(.CntH(Hour[7:4]),.CntL(Hour[3:0]),.nCR(nCR),.EN(Hour_EN),.CP(CP_1Hz));
assign Hour_EN = Adj_Hour? Vdd:((Minute==8'h59)&&(Second==8'h59));
//=====================================
//============数码管显示=================
SEG7_LUT D0(.oSEG(SEG),.CP(CLK_50),.light(SEL),.BCD({Hour,Minute}));
//=====================================
always@(EN or CP_1Hz)
begin
if(EN&&CP_1Hz) begin secLED<=1'b1; end
else begin secLED<=1'b0;end
end
endmodule

正如您所看到的，我使用了“保持层次结构”约束，但仍然得到Xst：1290警告说我的块未连接以及随之而来的许多其他警告。

检查我的RTL Schematic后，我发现我的所有模块都被排除在外！由于这个原因，我的整个项目无法进行。