Question

我想在VHDL中实现序列化器/反序列化器（SerDes）。实际上，它更像是一个简单的移位寄存器。移位寄存器存储一个值并移位以将信息从并行转换为串行。寄存器的输出为16位。它具有16位并行输入，这使我们可以向寄存器加载新值。加载输入允许在时钟的下降沿到来时加载新值。

此外，我还制作了一个testBench，将两个SerDes组件连接在一起以实现某种循环。不幸的是，我不知道为什么当我从并行输入发送值为“ 1234”的数据时，在并行输出waveform testBench中收到“ 3412”。

在我的代码下面：

SerDes.vhd：

apiVersion: batch/v1
kind: Job
metadata:
  name: kio
  namespace: kmlflow
  labels:
    app: kio
    name: kio
spec:
  template:
    metadata:
      labels:
        app: kio
        name: kio
    spec:
      containers:
      - name: kio-ingester
        image: MY_IMAGE
        command: ["/opt/bin/kio"]
        args: ["some", "args"]
        imagePullPolicy: Always
      restart: Never
  backoffLimit: 4

SERDESTestbench.vhd：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SerDes is
    generic ( 
        Dbits : integer := 16
           );   
    Port (
           serial_clk : in STD_LOGIC;
           clk        : in STD_LOGIC;
           rstn       : in STD_LOGIC;
           load : in STD_LOGIC;
           enable : in STD_LOGIC;
           serial_in : in STD_LOGIC;
           parallel_in : in STD_LOGIC_VECTOR(Dbits-1 downto 0);
           dout : out STD_LOGIC;
           parallel_out : out STD_LOGIC_VECTOR(Dbits-1 downto 0)
          );
end SerDes;

architecture Behavioral of SerDes is

signal rx_counter         : integer   := 0 ;
signal shift_reg : STD_LOGIC_VECTOR(Dbits-1 downto 0);
type   TYPE_STATE is (Idle,ShiftIn); 
signal CURRENT_STATE      : TYPE_STATE := Idle;
signal serial_clock_D : STD_LOGIC := '0';

begin

serialization : process(serial_clk,rstn)  --Envoyer une donnée parallèle et la récupérer sur la sortie série

begin 

    if (rstn = '0') then
        shift_reg <= (others => '0');
        rx_counter <= 0;
        serial_clock_D <= '0';
        CURRENT_STATE <= Idle;

    elsif (clk = '1' and clk'event) then     
            case CURRENT_STATE is 

                when Idle =>
                    if (enable = '1') then
                        CURRENT_STATE <= ShiftIn;
                    else
                        CURRENT_STATE <= Idle;     
                    end if;
                    if (load = '1') then
                        shift_reg <= parallel_in;
                    end if;
                    parallel_out <=  shift_reg;
                    rx_counter <= 0;

                when ShiftIn =>       
                      if(serial_clk = '1' and serial_clock_D = '0') then  
                        shift_reg <=  shift_reg(14 downto 0) & serial_in;                            
                      end if;
                       if (rx_counter = Dbits-1) then
                            CURRENT_STATE <= Idle;
                       else 
                            rx_counter <= rx_counter + 1;
                       end if;
            end case;
    end if;
end process;

dout <= shift_reg(15); 

end Behavioral;

问：序列化器/反序列化器问题

0 个答案: