VHDL fullAdder仿真？

Question

考虑以下代码：

entity FA is
port(X,Y:in bit;
cin : bit:='0';
sum:out bit;
cout : out bit); --this--
end FA;

architecture Data_flow of FA is
signal S1 , S2 : bit;
begin
S2<=S1 and cin;
S1<=X xor Y;
sum<=S1 xor cin;
cout<=S2 or(X and Y);
end Data_flow;

entity testBench is
end testBench;

architecture BA of testBench is
signal X,Y,cin,sum,cout:bit;
component FA port(X,Y:in bit;
cin:in bit:='0';
sum:out bit;
cout:out bit);
end component;
for all : FA use entity FA(Data_flow);
end for;
begin
EUT:FA port map(X,Y,cin,sum,cout);
X<='0','1' after 4ns;
Y<='0','1' after 2ns,'0' after 4ns,'1' after 6ns;
cin <='0','1' after 1ns,'0' after 2ns,'1' after 3ns,'0' after 4ns,'1'after 5ns,'0'after 6ns;
end BA;

我想用VHDL模拟此代码以创建fullAdder模拟。

我尝试了很多次，但是我无法获得目标视图。