Question

我想知道是否可以将以下代码放入for循环中，以便可以对代码进行参数化。谢谢。

always@(*) begin
if (exist_reg[0] == 'd0) begin
    nth_empty_location_descending = 'd1; // specify
end
else if (exist_reg[1] =='d0) begin
    nth_empty_location_descending = 'd2;
end
else if (exist_reg[2] =='d0) begin
    nth_empty_location_descending = 'd4;
end
else if (exist_reg[3] =='d0) begin
    nth_empty_location_descending = 'd8;
end
else if (exist_reg[4] =='d0) begin
    nth_empty_location_descending = 'd16;
end
else if (exist_reg[5] =='d0) begin
    nth_empty_location_descending = 'd32;
end
else if (exist_reg[6] =='d0) begin
    nth_empty_location_descending = 'd64;
end
else if (exist_reg[7] =='d0) begin
    nth_empty_location_descending = 'd128;
end
else if (exist_reg[8] =='d0) begin
    nth_empty_location_descending = 'd256;
end
else if (exist_reg[9] =='d0) begin
    nth_empty_location_descending = 'd512;
end
else begin
    nth_empty_location_descending = 'd0;
end
end

基本上，它是在检查“ exist_reg”位，如果遇到从左到右的任何位为零，则它将使“ nth_empty_location_descending”寄存器中的该位上升（还有更好的方法吗？）。现在，我想为寄存器的宽度创建参数化代码。当前，它是10位硬编码代码。谢谢专家。

Answer 1

首先，最好的解决方案可能是使用... export default { name: 'something', props: { genre: { type: String, required: true, }, }, ...语句而不是if / else链：

casez

但是，如果您坚持要这样做，则有一个基于循环的解决方案：

always@(*) begin
   casez (exist_reg)
     10'b?????????0:  nth_empty_location_descending1 = 'd1;
     10'b????????01:  nth_empty_location_descending1 = 'd2;
     10'b???????011:  nth_empty_location_descending1 = 'd4;
     10'b??????0111:  nth_empty_location_descending1 = 'd8;
     10'b?????01111:  nth_empty_location_descending1 = 'd16;
     10'b????011111:  nth_empty_location_descending1 = 'd32;
     10'b???0111111:  nth_empty_location_descending1 = 'd64;
     10'b??01111111:  nth_empty_location_descending1 = 'd128;
     10'b?011111111:  nth_empty_location_descending1 = 'd256;
     10'b0111111111:  nth_empty_location_descending1 = 'd512;
     default       :  nth_empty_location_descending1 = 'd0;
   endcase // casez (exist_reg)
end // always@ (*)

Answer 2

parameter WIDTH = 10;
reg [WIDTH-1:0] exist_reg, nth_empty_location_descending2;
integer ii;
always @* begin
   nth_empty_location_descending2 = 0;
   for(ii=0;ii<WIDTH;ii=ii+1)
      if (exist_reg[j] == 1'b0 && nth_empty_location_descending2 == 0)
         nth_empty_location_descending2[ii] = 1'b1;
  end

在SystemVerilog中

  parameter WIDTH = 10;
  logic [WIDTH-1:0] exist_reg, nth_empty_location_descending2;
  always_comb begin
     nth_empty_location_descending2 = 0;
     for(int ii=0;ii<WIDTH;ii++)
        if (exist_reg[j] == 1'b0) begin
           nth_empty_location_descending2[ii] = 1'b1;
           break;
        end
    end

在For Loop Verilog中嵌套IF

2 个答案: