如何在不使用时钟的情况下在Verilog中生成PWL或脉冲

Question

我正在处理一段代码，其中我需要根据条件生成输出-

1. if input is X/Z output should be X. 2. if input is 0 output should be 0 with a delay of 0.75us. 3. if input is 1 output should be 5 high going pulses of 1.5us with 50% duty cycle with a delay of 0.75us. 我很困惑如何用verilog编写它？

Answer 1

您可以为此使用SystemVerilog的fork/join_none

logic in, out;

    always begin
               fork 
                  case (in)
                    0: out <= #0.75us 0;
                    1: repeat (5) begin
                           #0.75us out <= 1; 
                           #0.75us out <= 0; 
                          end
                    default: out <= 'x;
                   endcase
                join_none;
                @in
                disable fork; // kill repeat loop if still active
             end