Question

我想在verilog中编译一个程序但是有一个基本的错误。我无法弄清楚是什么。第一个模块：

 module inst_line_buf    (from_LS,clk,fetch_ctrl,dec_ctrl,hmic_ctrl,branch_ctrl,to_if1,to_if2,flush_ctrl);
  //from local store and all the control signals defined. to_if sends 2 insts to fetch
  input from_LS, clk, fetch_ctrl, dec_ctrl, hmic_ctrl, branch_ctrl;
  output to_if1,to_if2;
  output flush_ctrl;
  // 16 instructions of 32 bits each.
  wire [511:0] from_LS;
  wire fetch_ctrl;
  // dec_ctrl - 1 bit
  // 0 : will tell if 2 instructions given to it are structurally dependent.
  wire dec_ctrl;
  // hmic_ctrl - 4 bits
  // 0 : whether to stall sending the instructions.
  // 1:3 : how many cycles to stall.
  wire [3:0] hmic_ctrl;
  // branch_ctrl - 14 bits
  // 0 : whether to issue from buffer 1 or buffer 2, whether branch is taken or not.
  // 1:13 : branch address. Get and store in buffer 2.
  wire [13:0] branch_ctrl;

  // to_if - 64 bits
  // 0:63 : 2 instructions to inst fetch.
  reg [31:0] to_if1;
  reg [31:0] to_if2; 
  // flush_ctrl - 1 bit
  // To three buffers in main prog, whether to flush the buffers or not.
  reg flush_ctrl;

  //pc is program counter
  reg [12:0] pc;
  // ilb stores 16 32 bit instructions from from_LS
  reg [31:0] ilb[0:15];
  // ilb1 is the buffer which stores all the branch instructions
  reg [31:0] ilb1[0:15];
  //buffer_bit - 1 bit
  // buffer_bit act like a vlid bit which helps in selecting appropriate buffer
  reg buffer_bit;
  integer a;
  integer count1,count2;

  initial
  begin
    count1 = 0;
    count2=0;
    flush_ctrl=0;
    buffer_bit=0;
    a=hmic_ctrl[3:1];
    ilb=from_LS[511:0];
    program_counter pctr (
     .clk(clk),
     .reset(0),
     .offset(branch_ctrl[13:1]),
     .mux_select(branch_ctrl[0]),
     .pc1(pc)
   );
  end

  always (@posedge clk)
  begin
    if(!dec_ctrl && !hmic_ctrl[0] && !branch_ctrl[0])
     begin
        if(buffer_bit==0)
          begin
            to_if1<=ilb[511-(count1*32)];
            to_if2<=ilb[511-((count1+1)*32)];
            count1<=count1+1;
          end
        else  
          begin
            to_if1<=ilb1[511-(count2*32)];
            to_if2<=ilb1[511-((count2+1)*32)];
            count2<=count2+1;
          end
      end
    else if (branch_ctrl[0])
      begin
        flush_ctrl<=1; // to flush the 3 buffer.
        // flush self.
      end 

    else if(dec_ctrl)
      begin
       if(buffer_bit==0)
         count1<=count1-1;
        else
          count2<=count2-1;
        //to_if1= opcode-nop;
        //to_if2= opcode-nop;
      end
    else if(hmic_ctrl[0])
      begin
        for (i=0;i<=a;i=i+1)
          begin
            //to_if1= opcode-nop;
            //to_if2= opcode-nop;
          end
      end
  end
endmodule

第二单元：

module program_counter (
  input wire clk, reset, mux_select,
  input wire [12:0] offset,
  output reg [12:0] pc1
);    //mux_select-> 1 bit
// offset is obtained from branch.

always @ (posedge clk)
if (!reset)
  begin
  if (!mux_select)
    pc1<= pc1+8;
  else
    pc1<=pc1+offset;
  end
else
  pc1<=0;
endmodule

我遇到了以下错误：

Error: C:/Modeltech_pe_edu_10.0/examples/COMP ARC/inst_line_buf.v(66): Undefined          variable: program_counter.
 Error: C:/Modeltech_pe_edu_10.0/examples/COMP ARC/inst_line_buf.v(66): near "pctr":     syntax error, unexpected IDENTIFIER
Error: C:/Modeltech_pe_edu_10.0/examples/COMP ARC/inst_line_buf.v(68): near "(":     syntax error, unexpected '('

Answer 1

你有一些错误的声明：

公交车应该使用[]，而不是()。例如，请尝试branch_ctrl[13:1]而不是branch_ctrl(13:1)
您的offset端口需要大小
对顺序逻辑使用非阻塞分配
您可以使用verilog-2001样式端口声明来保存输入

这是您的代码的编辑版本。它会编译，但我觉得它不能正常工作，因为我没有你的顶级模块的完整版本：

module inst_line_buf (
   input wire from_LS,clk,fetch_ctrl,dec_ctrl,
   hmic_ctrl,to_if1,to_if2,flush_ctrl,
   input wire [13:0] branch_ctrl,
   output wire [12:0] pc
);

   program_counter pctr (
     .clk(clk),
     .reset(0),
     .offset(branch_ctrl[13:1]),
     .mux_select(branch_ctrl[0]),
     .pc1(pc)
   );

endmodule


module program_counter (
  input wire clk, reset, mux_select,
  input wire [12:0] offset,
  output reg [12:0] pc1
);

 always @ (posedge clk)
 if (!reset)
   begin
     if (!mux_select)
       pc1 <= pc1+8;
     else
       pc1 <= pc1+offset;
   end
 else
   pc1 <= 0;

endmodule

另外，请确保您的模块实例化超出任何initial或always块。

verilog基本编译器错误

1 个答案: