释放键后如何使键生成,7段显示,输出保持不变? [VHDL]

时间:2019-03-29 19:57:50

标签: vhdl fpga intel-fpga

我正在尝试从键盘上读取输入,我希望用户输入的数字在7段显示器上保持不变,直到按下另一个键为止。

当前,松开键时7段显示输出消失。如何使7段显示输出保持不变?

这是我的完整代码:

ARCHITECTURE Behavioral OF keypad IS 

SIGNAL  t1, t2, t3, t4: STD_LOGIC_VECTOR (1 TO 4) := "1111";
SIGNAL curr : STD_LOGIC_VECTOR(1 TO 4) := "0111";
BEGIN 
proc_1: PROCESS
BEGIN

WAIT UNTIL rising_edge(clk);

        IF curr <= "0111" THEN  t1<= row ;

        curr <= "1011";

        ELSIF curr <= "1011" THEN t2<= row ;

        curr <= "1101";

        ELSIF curr <= "1101" THEN t3<= row ;

        curr <= "1110";

        ELSIF curr <= "1110" THEN t4<= row ;

        curr <= "0111";

        ELSE 
         curr <= "0111";
    END IF ;
END PROCESS ;
    proc_2: PROCESS (t1, t2, t3, t4)
    BEGIN
    hit <= '1';
    IF t1(1) = '0' THEN sevenseg <= "1001111" ; --1
    ELSIF t1(2) = '0' THEN sevenseg <= "1001100" ;  --4
    ELSIF t1(3) = '0' THEN sevenseg <= "0001111" ;  --7
    ELSIF t1(4) = '0' THEN sevenseg <= "1111111" ;  --*
    ELSIF t2(1) = '0' THEN sevenseg <= "0010010" ;  --2
    ELSIF t2(2) = '0' THEN sevenseg <="0100100" ;   --5
    ELSIF t2(3) = '0' THEN sevenseg <= "0000000" ; --8
    ELSIF t2(4) = '0' THEN sevenseg <= "0000001" ; --0
    ELSIF t3(1) = '0' THEN sevenseg <= "0000110" ;  --3
    ELSIF t3(2) = '0' THEN sevenseg <= "0100000" ;  --6
    ELSIF t3(3) = '0' THEN sevenseg <= "0000100" ;  --9
    ELSIF t3(4) = '0' THEN sevenseg <= "1111111" ;  --#
    ELSIF t4(1) = '0' THEN sevenseg <= "0001000" ;  --A
    ELSIF t4(2) = '0' THEN sevenseg <= "1111111" ;  --B
    ELSIF t4(3) = '0' THEN sevenseg <= "0110001" ;  --C
    ELSIF t4(4) = '0' THEN sevenseg <= "1111111" ;  --D
    ELSE 
        hit <= '0'; 
    END IF;
    END PROCESS;
    col <= curr ;       
END Behavioral ;

0 个答案:

没有答案
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