给自己分配信号失败

Question

此代码未按预期将8映射到paddle_out：

 entity GAME is
  port(
      --L : in std_logic;
      --R : in std_logic;
      clk    : in std_logic;
      paddle_out : out unsigned (9 downto 0)
  );    
end;

architecture GAME_ARCH of GAME is
    signal paddle : unsigned (9 downto 0) := 10d"8";
begin

  process (clk) is
  begin
    if rising_edge(clk) then

      -- PADDLE (changes 'paddle')
      --if L = '1' and R = '0' then
        --paddle <= paddle - 1 when paddle >= 63;
      --elsif L = '0' and R = '1' then
        --paddle <= paddle + 1 when paddle <= 495; -- 575-80 (rightmost edge of screen minus width of paddle)
      --end if;

    paddle_out <= paddle;
    paddle <= paddle + 0;

    end if;
  end process;
end;

如果我删除paddle <= paddle，这似乎可行。

这是怎么回事？

测试模块：

entity TEST is
   port(test : out unsigned(9 downto 0));
end;

architecture test_arch of TEST is

component HSOSC is
    generic (CLKHF_DIV : String := "0b00");
    port (
        CLKHFPU : in  std_logic := '1';
        CLKHFEN : in  std_logic := '1';
        CLKHF   : out std_logic := 'X'
    );
end component;

component GAME is
   port(
      clk : in std_logic;
      paddle_out : out unsigned (9 downto 0)
  );
end component;

    signal clock : std_logic;
begin
    my_clock : HSOSC port map('1', '1', clock);
    my_game  : GAME  port map(clock, test);
end;