Question

我已经创建了一个有限状态机/数据路径，正在ModelSim中进行调试。状态为“加载”，“增量”和“完成”。这些状态似乎进展良好，但是countx和county（内部信号）没有在增量状态下递增，因此vga_x和vga_y输出未分配。

我尝试将countx和county信号从逻辑更改为reg，但这没有任何区别。还尝试将输出信号设置为阻塞，因为我希望在它们以相同状态递增后将countx和county分配给输出。

module fillscreen(input logic clk, input logic rst_n, input logic [2:0] colour,
              input logic start, output logic done,
              output logic [7:0] vga_x, output logic [6:0] vga_y,
              output logic [2:0] vga_colour, output logic vga_plot);

 enum logic [1:0] {Load = 2'b00, Increment = 2'b01, Out = 2'b10, Finish = 2'b11} state, next_state;
 reg[7:0] countx;
 reg [6:0] county;

 always @ (posedge clk) begin
    state = Load;
    case(state)

    Load: begin
           if(rst_n == 0) 
            next_state <= Load; 
        else if (start == 1) 
            next_state <= Increment;
        else begin
        next_state <= Load; end
    //initialize counter
    countx <= 0;    
    county <= 0; end

    Increment: begin
        if(rst_n == 0) 
            next_state <= Load;
        else if (county < 119 && countx < 159) begin
            county <= county+1; 
            next_state <= Increment; end                
        else if (countx < 159) begin
            countx <= countx +1;
            next_state <= Increment; end
        else begin 
            next_state <= Finish;end
    //output            
    vga_y = county;
    vga_x = countx;
    vga_colour = countx % 8;            
    vga_plot = 1;
    end
    Finish: begin
        done <= 1;          
        if(rst_n == 0) 
            next_state <= Load; 
        else begin
            next_state <= Finish; end
    end
    default: begin 
        vga_y = county;
        vga_x = countx;
        done = 0;
        vga_plot = 0;
    end
    endcase
    state = next_state;
end  
endmodule

Answer 1

注意始终会从头到尾进行程序评估。您的第一行是

always @(posedge clk) begin
state = Load;
...

当块执行并从中擦除先前设置的状态时，将状态设置为“加载”

state = next_state;

这意味着每个时钟周期，case（state）块都会沿着Load路径移动。

我建议将FSM状态设置在其自己的always块中，以简化代码。

always @(posedge clk) begin
    if(!rst_n) begin
        state <= Load;
    end
    else begin
        state <= next_state;
    end
end

通过这种方式，您可以专注于使用“状态”作为输入，而将“ next_state”作为原始始终块的输出。

FSM：看不到波形输出

1 个答案: