VHDL:上限和下限除以两个整数常量

时间:2019-06-16 11:50:06

标签: vhdl

在VHDL中,我正在寻找一种方法来获取一个实体的两个整数参数,将一个整数除以另一个作为浮点数,然后找到该浮点数比率的下限和上限,然后将其存储为vhdl整数常量。

library ieee;
use     ieee.std_logic_1164.all;

entity something is
    generic(
        N: natural := 4;
        M: natural := 150
    );
    port(
        sys_clk     :in  std_logic;
        sys_rst     :in  std_logic;

        datai       :in  std_logic_vector(M-1 downto 0);
        datao       :out std_logic_vector(N-1 downto 0)
    );
end entity;


architecture rtl is something is
    --how to calculate ceiling of  M / N?
    constant ratio_ceiling :integer := integer(real(M)/real(N));

    --how to calculate floor of M / N?
    constant ratio_floor   :integer := integer(real(M)/real(N));

begin

end architecture;

2 个答案:

答案 0 :(得分:1)

代码:

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.math_real.all;

entity something is
    generic(
        N: natural := 4;
        M: natural := 150
    );
    port(
        sys_clk     :in   std_logic;
        sys_rst     :in   std_logic;

        datai       :in   std_logic_vector(M-1 downto 0);
        datao       :out  std_logic_vector(N-1 downto 0)
    );
end entity;


architecture rtl of something is
    --how to calculate ceiling of  M / N
    constant ratio_ceiling :integer := integer(ceil(real(M)/real(N)));

    --how to calculate floor of M / N
    constant ratio_floor   :integer := integer(floor(real(M)/real(N)));

begin

    process
    begin
        report "ceil:  " & integer'image(ratio_ceiling);
        report "floor: " & integer'image(ratio_floor);
        wait;
    end process;
end architecture;

输出:

C:\something> ghdl -a --std=08 --ieee=synopsys --work=work something.vhd

C:\something> ghdl --elab-run --std=08 --ieee=synopsys something --vcd=waves.vcd --ieee-asserts=disable

something.vhd:33:12:@0ms:(report note): ceil:  38
something.vhd:34:12:@0ms:(report note): floor: 37

答案 1 :(得分:0)

不确定您的问题是什么,代码似乎正确。如果您希望避免所有类型转换和转换,则可以使用

    var mTextViewResult : TextView by lazy { findViewById(R.id.tvResult) }

    onCreate(...) {...}

VHDL整数将四舍五入,因此效果很好。

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