在VHDL中使用D型触发器的微机检测器

Question

我正在尝试设计一种Mealy机器，该机器使用D触发器检测VHDL中的序列“ 001”。这是代码和测试台，都可以正常编译，但是当我使用包含序列的输入运行它时，没有应有的输出。你可以帮帮我吗？谢谢！

FLIP FLOP D

library IEEE;
use IEEE.std_logic_1164.all;

entity ffd is 
    port(
        clk: in std_logic;
        rst: in std_logic;
        ena: in std_logic;
        D:   in std_logic;
        Q : out std_logic
        );
    end;

architecture ffd_arq of ffd is
begin

process(clk) 
    begin
    if rising_edge(clk) then
        if rst ='1' then 
        Q <= '0';
        elsif ena ='1' then
        Q <= D; 
        end if;
    end if;
end process;
    
    
end;

探测器

library IEEE;
use IEEE.std_logic_1164.all;
use work.all;

entity detector is
port(
Input: in std_logic;
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
q: out std_logic
);
end;

architecture detector_arq of detector is
signal D0_aux, D1_aux: std_logic;
signal Q0, Q1: std_logic;
signal I_aux: std_logic;
begin
I_aux <= Input;
-- Funcion D0;
D0_aux <= ((not I_aux) and (not Q0) and (not Q1)) or (I_aux and Q0) or (I_aux and Q1);
-- Funcion D1;
D1_aux <= (not I_aux) and Q0;
--Salida
q <= I_aux and Q1;

-- flip-flop 0
ffd_0: entity work.ffd
            port map(
                    clk => clk,
                    rst => rst,
                    ena => ena,
                    D => D0_aux,
                    Q => Q0
            );

-- flip-flop 1
ffd_1: entity work.ffd
            port map(
                    clk => clk,
                    rst => rst,
                    ena => ena,
                    D => D1_aux,
                    Q => Q1
            );


end;

探测器探伤

library IEEE;
use IEEE.std_logic_1164.all;
use work.all;

entity detector_tb is
end;

architecture detector_tb_arq of detector_tb is

    component detector is
    port(
    Input: in std_logic;
    clk: in std_logic;
    rst: in std_logic;
    ena: in std_logic;
    q: out std_logic
    );
    end component;

    signal  clk_tb: std_logic := '0';
    signal  rst_tb: std_logic := '1';
    signal  ena_tb: std_logic := '1';
    
    signal q_tb: std_logic;
    signal I_aux: std_logic;


begin

        clk_tb <= not clk_tb after 20 ns;
        rst_tb <= '0' after 500 ns;
        --I_aux <= '0','1' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '0' after 80 ns; --NO '001'
        --I_aux <= '0','1' after 40 ns, '0' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns; --SEQUENCE 001 1 TIME
        I_aux <= '0','1' after 40 ns, '0' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '1' after 110 ns,'0' after 120 ns; --SEQUENCE001 2 TIMES

        
        DUT: detector
        port map(
                Input => I_aux,
                clk => clk_tb,
                rst => rst_tb,
                ena => ena_tb,
                q => q_tb
                );

end;