VHDL奇怪的语句错误（语法）

Question

我们的VHDL代码中有一个非常奇怪但简单的if语句错误，现在我们已经尝试了我们能想到的所有内容，但程序仍然抱怨语法错误（靠近第一个“何时”） ）在声明中。

    ALUsource <= '0';
            with FuncCode select
                    ALUcontrol <=   "10" when "0x20",
                                    "10" when "0x22",
                                    "00" when "0x24",
                                    "01" when "0x25",
                                    "11" when "0x2A",
                                    "00" when others;

            with FuncCode select
                    SubFlag <=     '1' when "0x22",
                                   '0' when others;

            with FuncCode select   
                    W_ena <=       '1' when "0x20",
                                   '1' when "0x22",
                                   '1' when "0x24",
                                   '1' when "0x25",
                                   '1' when "0x2A",
                                   '0' when others;


    when OPcode /= "000000"
            with OPcode select
                    ALUcontrol <=   "10" when "0x08",
                                    "11" when "0x0A",
                                    "00" when others;

Answer 1

正如之前的评论所说，这个例子并不完整，因此很难说出错误在哪里，但我猜测并建议写作

when OPcode /= "000000" =>

而不是

when OPcode /= "000000"